/external/mesa3d/src/mesa/drivers/dri/i965/ |
intel_upload.c | 48 intel_upload_finish(struct brw_context *brw) 50 if (!brw->upload.bo) 53 drm_intel_bo_unmap(brw->upload.bo); 54 drm_intel_bo_unreference(brw->upload.bo); 55 brw->upload.bo = NULL; 56 brw->upload.next_offset = 0; 83 intel_upload_space(struct brw_context *brw, 91 offset = ALIGN_NPOT(brw->upload.next_offset, alignment); 92 if (brw->upload.bo && offset + size > brw->upload.bo->size) [all...] |
brw_pipe_control.c | 72 gen7_cs_stall_every_four_pipe_controls(struct brw_context *brw, uint32_t flags) 74 if (brw->gen == 7 && !brw->is_haswell) { 77 brw->pipe_controls_since_last_cs_stall = 0; 82 if (++brw->pipe_controls_since_last_cs_stall == 4) { 83 brw->pipe_controls_since_last_cs_stall = 0; 97 brw_emit_pipe_control_flush(struct brw_context *brw, uint32_t flags) 99 if (brw->gen >= 6 && 112 brw_emit_pipe_control_flush(brw, (flags & PIPE_CONTROL_CACHE_FLUSH_BITS) | 117 if (brw->gen >= 8) [all...] |
brw_urb.c | 100 static bool check_urb_layout(struct brw_context *brw) 102 brw->urb.vs_start = 0; 103 brw->urb.gs_start = brw->urb.nr_vs_entries * brw->urb.vsize; 104 brw->urb.clip_start = brw->urb.gs_start + brw->urb.nr_gs_entries * brw->urb.vsize; 105 brw->urb.sf_start = brw->urb.clip_start + brw->urb.nr_clip_entries * brw->urb.vsize [all...] |
brw_gs_surface_state.c | 39 brw_upload_gs_pull_constants(struct brw_context *brw) 41 struct brw_stage_state *stage_state = &brw->gs.base; 44 struct brw_program *gp = (struct brw_program *) brw->geometry_program; 50 const struct brw_stage_prog_data *prog_data = brw->gs.base.prog_data; 52 _mesa_shader_write_subroutine_indices(&brw->ctx, MESA_SHADER_GEOMETRY); 54 brw_upload_pull_constants(brw, BRW_NEW_GS_CONSTBUF, &gp->program, 61 .brw = BRW_NEW_BATCH | 70 brw_upload_gs_ubo_surfaces(struct brw_context *brw) 72 struct gl_context *ctx = &brw->ctx; 82 struct brw_stage_prog_data *prog_data = brw->gs.base.prog_data [all...] |
brw_tcs_surface_state.c | 39 brw_upload_tcs_pull_constants(struct brw_context *brw) 41 struct brw_stage_state *stage_state = &brw->tcs.base; 44 struct brw_program *tcp = (struct brw_program *) brw->tess_ctrl_program; 50 const struct brw_stage_prog_data *prog_data = brw->tcs.base.prog_data; 52 _mesa_shader_write_subroutine_indices(&brw->ctx, MESA_SHADER_TESS_CTRL); 54 brw_upload_pull_constants(brw, BRW_NEW_TCS_CONSTBUF, &tcp->program, 61 .brw = BRW_NEW_BATCH | 70 brw_upload_tcs_ubo_surfaces(struct brw_context *brw) 72 struct gl_context *ctx = &brw->ctx; 82 struct brw_stage_prog_data *prog_data = brw->tcs.base.prog_data [all...] |
brw_tes_surface_state.c | 39 brw_upload_tes_pull_constants(struct brw_context *brw) 41 struct brw_stage_state *stage_state = &brw->tes.base; 44 struct brw_program *dp = (struct brw_program *) brw->tess_eval_program; 50 const struct brw_stage_prog_data *prog_data = brw->tes.base.prog_data; 52 _mesa_shader_write_subroutine_indices(&brw->ctx, MESA_SHADER_TESS_EVAL); 54 brw_upload_pull_constants(brw, BRW_NEW_TES_CONSTBUF, &dp->program, 61 .brw = BRW_NEW_BATCH | 70 brw_upload_tes_ubo_surfaces(struct brw_context *brw) 72 struct gl_context *ctx = &brw->ctx; 82 struct brw_stage_prog_data *prog_data = brw->tes.base.prog_data [all...] |
brw_binding_tables.c | 54 reserve_hw_bt_space(struct brw_context *brw, unsigned bytes) 65 if (brw->hw_bt_pool.next_offset + bytes >= brw->hw_bt_pool.bo->size - 128) { 66 gen7_reset_hw_bt_pool_offsets(brw); 69 uint32_t offset = brw->hw_bt_pool.next_offset; 77 brw->hw_bt_pool.next_offset += ALIGN(bytes, 64); 89 brw_upload_binding_table(struct brw_context *brw, 96 if (stage_state->bind_bo_offset == 0 && brw->gen < 9) 104 brw, &stage_state->surf_offset[ 106 brw->shader_time.bo, 0, BRW_SURFACEFORMAT_RAW [all...] |
gen6_urb.c | 50 gen6_upload_urb(struct brw_context *brw, unsigned vs_size, 54 int total_urb_size = brw->urb.size * 1024; /* in bytes */ 55 const struct gen_device_info *devinfo = &brw->screen->devinfo; 74 brw->urb.nr_vs_entries = ROUND_DOWN_TO(nr_vs_entries, 4); 75 brw->urb.nr_gs_entries = ROUND_DOWN_TO(nr_gs_entries, 4); 77 assert(brw->urb.nr_vs_entries >= 79 assert(brw->urb.nr_vs_entries % 4 == 0); 80 assert(brw->urb.nr_gs_entries % 4 == 0); 87 ((brw->urb.nr_vs_entries) << GEN6_URB_VS_ENTRIES_SHIFT)); 89 ((brw->urb.nr_gs_entries) << GEN6_URB_GS_ENTRIES_SHIFT)) [all...] |
brw_cs.h | 33 brw_upload_cs_prog(struct brw_context *brw);
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brw_gs_state.c | 39 brw_upload_gs_unit(struct brw_context *brw) 43 gs = brw_state_batch(brw, AUB_TRACE_GS_STATE, 44 sizeof(*gs), 32, &brw->ff_gs.state_offset); 49 if (brw->ff_gs.prog_active) { 50 gs->thread0.grf_reg_count = (ALIGN(brw->ff_gs.prog_data->total_grf, 16) / 54 brw_program_reloc(brw, 55 brw->ff_gs.state_offset + 57 brw->ff_gs.prog_offset + 68 brw->ff_gs.prog_data->urb_read_length; 71 gs->thread4.nr_urb_entries = brw->urb.nr_gs_entries [all...] |
gen8_surface_state.c | 46 gen8_allocate_surface_state(struct brw_context *brw, 49 uint32_t *surf = __brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, 64 gen8_emit_null_surface_state(struct brw_context *brw, 70 uint32_t *surf = gen8_allocate_surface_state(brw, out_offset, -1); 80 gen8_init_vtable_surface_functions(struct brw_context *brw) 82 brw->vtbl.update_renderbuffer_surface = brw_update_renderbuffer_surface; 83 brw->vtbl.emit_null_surface_state = gen8_emit_null_surface_state;
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brw_state_dump.c | 73 batch_out(struct brw_context *brw, const char *name, uint32_t offset, 77 batch_out(struct brw_context *brw, const char *name, uint32_t offset, 80 uint32_t *data = brw->batch.bo->virtual + offset; 91 batch_out64(struct brw_context *brw, const char *name, uint32_t offset, 94 uint32_t *tmp = brw->batch.bo->virtual + offset; 123 static void dump_vs_state(struct brw_context *brw, uint32_t offset) 126 struct brw_vs_unit_state *vs = brw->batch.bo->virtual + offset; 128 batch_out(brw, name, offset, 0, "thread0\n"); 129 batch_out(brw, name, offset, 1, "thread1\n"); 130 batch_out(brw, name, offset, 2, "thread2\n") [all...] |
gen6_sampler_state.c | 34 upload_sampler_state_pointers(struct brw_context *brw) 42 OUT_BATCH(brw->vs.base.sampler_offset); /* VS */ 43 OUT_BATCH(brw->gs.base.sampler_offset); /* GS */ 44 OUT_BATCH(brw->wm.base.sampler_offset); 51 .brw = BRW_NEW_BATCH |
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brw_state_batch.c | 38 brw_track_state_batch(struct brw_context *brw, 44 struct intel_batchbuffer *batch = &brw->batch; 46 if (!brw->state_batch_list) { 51 brw->state_batch_list = rzalloc_size(brw, sizeof(*brw->state_batch_list) * 55 brw->state_batch_list[brw->state_batch_count].offset = offset; 56 brw->state_batch_list[brw->state_batch_count].size = size [all...] |
genX_blorp_exec.c | 41 struct brw_context *brw = batch->driver_batch; local 43 intel_batchbuffer_begin(brw, n, RENDER_RING); 44 uint32_t *map = brw->batch.map_next; 45 brw->batch.map_next += n; 46 intel_batchbuffer_advance(brw); 55 struct brw_context *brw = batch->driver_batch; local 57 uint32_t offset = (char *)location - (char *)brw->batch.map; 58 if (brw->gen >= 8) { 59 return intel_batchbuffer_reloc64(&brw->batch, address.buffer, offset, 64 return intel_batchbuffer_reloc(&brw->batch, address.buffer, offset 76 struct brw_context *brw = batch->driver_batch; local 100 struct brw_context *brw = batch->driver_batch; local 112 struct brw_context *brw = batch->driver_batch; local 131 struct brw_context *brw = batch->driver_batch; local 171 struct brw_context *brw = batch->driver_batch; local 191 struct brw_context *brw = batch->driver_batch; local [all...] |
brw_conditional_render.c | 41 set_predicate_enable(struct brw_context *brw, 45 brw->predicate.state = BRW_PREDICATE_STATE_RENDER; 47 brw->predicate.state = BRW_PREDICATE_STATE_DONT_RENDER; 51 set_predicate_for_result(struct brw_context *brw, 63 brw_emit_pipe_control_flush(brw, PIPE_CONTROL_FLUSH_ENABLE); 65 brw_load_register_mem64(brw, 71 brw_load_register_mem64(brw, 90 brw->predicate.state = BRW_PREDICATE_STATE_USE_BIT; 98 struct brw_context *brw = brw_context(ctx); local 102 if (!brw->predicate.supported 136 struct brw_context *brw = brw_context(ctx); local [all...] |
brw_draw.c | 78 brw_set_prim(struct brw_context *brw, const struct _mesa_prim *prim) 80 struct gl_context *ctx = &brw->ctx; 100 if (hw_prim != brw->primitive) { 101 brw->primitive = hw_prim; 102 brw->ctx.NewDriverState |= BRW_NEW_PRIMITIVE; 104 if (reduced_prim[prim->mode] != brw->reduced_primitive) { 105 brw->reduced_primitive = reduced_prim[prim->mode]; 106 brw->ctx.NewDriverState |= BRW_NEW_REDUCED_PRIMITIVE; 112 gen6_set_prim(struct brw_context *brw, const struct _mesa_prim *prim) 114 const struct gl_context *ctx = &brw->ctx 447 struct brw_context *brw = brw_context(ctx); local 646 struct brw_context *brw = brw_context(ctx); local [all...] |
brw_state_upload.c | 386 brw_upload_initial_gpu_state(struct brw_context *brw) 392 if (!brw->hw_ctx) 395 if (brw->gen == 6) 396 brw_emit_post_sync_nonzero_flush(brw); 398 brw_upload_invariant_state(brw); 401 if (brw->gen >= 9) { 410 if (brw->gen >= 8) { 411 gen8_emit_3dstate_sample_pattern(brw); 429 brw_get_pipeline_atoms(struct brw_context *brw, 434 return brw->render_atoms [all...] |
brw_reset.c | 36 struct brw_context *brw = brw_context(ctx); local 46 assert(brw->hw_ctx != NULL); 52 if (brw->reset_count != 0) 55 err = drm_intel_get_reset_stats(brw->hw_ctx, &reset_count, &active, 64 brw->reset_count = reset_count; 73 brw->reset_count = reset_count; 81 brw_check_for_reset(struct brw_context *brw) 88 err = drm_intel_get_reset_stats(brw->hw_ctx, &reset_count, &active, 94 _mesa_set_context_lost_dispatch(&brw->ctx);
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brw_curbe.c | 76 static void calculate_curbe_offsets( struct brw_context *brw ) 78 struct gl_context *ctx = &brw->ctx; 80 const GLuint nr_fp_regs = (brw->wm.base.prog_data->nr_params + 15) / 16; 83 const GLuint nr_vp_regs = (brw->vs.base.prog_data->nr_params + 15) / 16; 110 if (nr_fp_regs > brw->curbe.wm_size || 111 nr_vp_regs > brw->curbe.vs_size || 112 nr_clip_regs != brw->curbe.clip_size || 113 (total_regs < brw->curbe.total_size / 4 && 114 brw->curbe.total_size > 16)) { 121 brw->curbe.wm_start = reg [all...] |
intel_buffers.c | 39 struct brw_context *const brw = brw_context(ctx); local 45 dri2InvalidateDrawable(brw->driContext->driDrawablePriv); 46 intel_prepare_render(brw); 55 struct brw_context *const brw = brw_context(ctx); local 61 dri2InvalidateDrawable(brw->driContext->driReadablePriv); 62 intel_prepare_render(brw);
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brw_clip_state.c | 38 upload_clip_vp(struct brw_context *brw) 40 struct gl_context *ctx = &brw->ctx; 43 vp = brw_state_batch(brw, AUB_TRACE_CLIP_VP_STATE, 44 sizeof(*vp), 32, &brw->clip.vp_offset); 57 brw_upload_clip_unit(struct brw_context *brw) 59 struct gl_context *ctx = &brw->ctx; 67 upload_clip_vp(brw); 69 clip = brw_state_batch(brw, AUB_TRACE_CLIP_STATE, 70 sizeof(*clip), 32, &brw->clip.state_offset); 74 clip->thread0.grf_reg_count = (ALIGN(brw->clip.prog_data->total_grf, 16) [all...] |
intel_batchbuffer.c | 84 intel_batchbuffer_reset_and_clear_render_cache(struct brw_context *brw) 86 intel_batchbuffer_reset(&brw->batch, brw->bufmgr, brw->has_llc); 87 brw_render_cache_set_clear(brw); 91 intel_batchbuffer_save_state(struct brw_context *brw) 93 brw->batch.saved.map_next = brw->batch.map_next; 94 brw->batch.saved.reloc_count = 95 drm_intel_gem_bo_get_reloc_count(brw->batch.bo) [all...] |
brw_ff_gs.c | 48 brw_codegen_ff_gs_prog(struct brw_context *brw, 59 c.vue_map = brw_vue_prog_data(brw->vs.base.prog_data)->vue_map; 66 brw_init_codegen(&brw->screen->devinfo, &c.func, mem_ctx); 75 if (brw->gen >= 6) { 138 brw_disassemble(&brw->screen->devinfo, c.func.store, 143 brw_upload_cache(&brw->cache, BRW_CACHE_FF_GS_PROG, 147 &brw->ff_gs.prog_offset, &brw->ff_gs.prog_data); 152 brw_ff_gs_state_dirty(const struct brw_context *brw) 154 return brw_state_dirty(brw, [all...] |
brw_gs.h | 38 brw_upload_gs_prog(struct brw_context *brw); 41 brw_gs_populate_key(struct brw_context *brw,
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