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  /toolchain/binutils/binutils-2.25/gas/testsuite/gas/mmix/
reg3-op.d 17 28: 330c20b0 cmpu \$12,\$32,176
reg3-op-r.d 19 28: 330c20b0 cmpu \$12,\$32,176
list-in-n.d 75 108: 3202df0b cmpu \$2,\$223,\$11
76 10c: 330c14cd cmpu \$12,\$20,205
list-in-r.d 75 108: 3202df0b cmpu \$2,\$223,\$11
76 10c: 330c14cd cmpu \$12,\$20,205
list-in-rn.d 75 108: 3202df0b cmpu \$2,\$223,\$11
76 10c: 330c14cd cmpu \$12,\$20,205
list-insns.d 73 108: 3202df0b cmpu \$2,\$223,\$11
74 10c: 330c14cd cmpu \$12,\$20,205
  /toolchain/binutils/binutils-2.25/gas/testsuite/gas/mips/
mips32-dsp.s 90 cmpu.eq.qb $6,$7
91 cmpu.lt.qb $7,$8
92 cmpu.le.qb $8,$9
mips64-dsp.s 26 cmpu.eq.ob $14,$15
27 cmpu.lt.ob $15,$16
28 cmpu.le.ob $16,$17
micromips@mips32-dsp.d 91 0+0140 <[^>]*> 00e6 0245 cmpu\.eq\.qb a2,a3
92 0+0144 <[^>]*> 0107 0285 cmpu\.lt\.qb a3,t0
93 0+0148 <[^>]*> 0128 02c5 cmpu\.le\.qb t0,t1
mips32-dsp.d 90 0+0140 <[^>]*> 7cc70011 cmpu\.eq\.qb a2,a3
91 0+0144 <[^>]*> 7ce80051 cmpu\.lt\.qb a3,t0
92 0+0148 <[^>]*> 7d090091 cmpu\.le\.qb t0,t1
mipsr6@mips32-dsp.d 91 0+0140 <[^>]*> 7cc70011 cmpu\.eq\.qb a2,a3
92 0+0144 <[^>]*> 7ce80051 cmpu\.lt\.qb a3,t0
93 0+0148 <[^>]*> 7d090091 cmpu\.le\.qb t0,t1
mips64-dsp.d 26 0+0040 <[^>]*> 7dcf0015 cmpu\.eq\.ob t6,t7
27 0+0044 <[^>]*> 7df00055 cmpu\.lt\.ob t7,s0
28 0+0048 <[^>]*> 7e110095 cmpu\.le\.ob s0,s1
  /external/llvm/test/MC/Mips/micromips-dsp/
valid.s 115 cmpu.eq.qb $1, $2 # CHECK: cmpu.eq.qb $1, $2 # encoding: [0x00,0x41,0x02,0x45]
116 cmpu.lt.qb $1, $2 # CHECK: cmpu.lt.qb $1, $2 # encoding: [0x00,0x41,0x02,0x85]
117 cmpu.le.qb $1, $2 # CHECK: cmpu.le.qb $1, $2 # encoding: [0x00,0x41,0x02,0xc5]
  /external/swiftshader/third_party/LLVM/test/MC/MBlaze/
mblaze_typea.s 44 # CHECK: cmpu
47 cmpu r1, r2, r3
  /external/llvm/test/MC/Mips/dsp/
valid.s 22 cmpu.eq.qb $20, $21 # CHECK: cmpu.eq.qb $20, $21 # encoding: [0x7e,0x95,0x00,0x11]
23 cmpu.lt.qb $22, $23 # CHECK: cmpu.lt.qb $22, $23 # encoding: [0x7e,0xd7,0x00,0x51]
24 cmpu.le.qb $24, $25 # CHECK: cmpu.le.qb $24, $25 # encoding: [0x7f,0x19,0x00,0x91]
  /external/llvm/test/MC/Mips/micromips-dspr2/
valid.s 141 cmpu.eq.qb $1, $2 # CHECK: cmpu.eq.qb $1, $2 # encoding: [0x00,0x41,0x02,0x45]
142 cmpu.lt.qb $1, $2 # CHECK: cmpu.lt.qb $1, $2 # encoding: [0x00,0x41,0x02,0x85]
143 cmpu.le.qb $1, $2 # CHECK: cmpu.le.qb $1, $2 # encoding: [0x00,0x41,0x02,0xc5]
  /toolchain/binutils/binutils-2.25/gas/testsuite/gas/m32r/
allinsn.s 158 .global cmpu
159 cmpu: label
160 cmpu fp,fp
m32rx.d 128 a0: 1f cd 8d 5d jmp fp \|\| cmpu fp,fp
129 a4: 1f cd 8d 5d jmp fp \|\| cmpu fp,fp
253 19c: 0d 5d d0 84 cmpu fp,fp \|\| rach a0,a1
254 1a0: 0d 5d d4 84 cmpu fp,fp \|\| rach a1,a1
allinsn.d 123 0+0098 <cmpu>:
124 98: 0d 5d f0 00 cmpu fp,fp \|\| nop
  /prebuilts/go/darwin-x86/src/cmd/compile/internal/s390x/
ssa.go 637 cmpu := gc.Prog(s390x.ACMPU)
638 cmpu.From.Reg = v.Args[1].Reg()
639 cmpu.From.Type = obj.TYPE_REG
640 cmpu.To.Reg = v.Args[2].Reg()
641 cmpu.To.Type = obj.TYPE_REG
681 cmpu := gc.Prog(s390x.ACMPU)
682 cmpu.From.Reg = v.Args[0].Reg()
683 cmpu.From.Type = obj.TYPE_REG
684 cmpu.To.Reg = v.Args[1].Reg()
685 cmpu.To.Type = obj.TYPE_RE
    [all...]
  /prebuilts/go/linux-x86/src/cmd/compile/internal/s390x/
ssa.go 637 cmpu := gc.Prog(s390x.ACMPU)
638 cmpu.From.Reg = v.Args[1].Reg()
639 cmpu.From.Type = obj.TYPE_REG
640 cmpu.To.Reg = v.Args[2].Reg()
641 cmpu.To.Type = obj.TYPE_REG
681 cmpu := gc.Prog(s390x.ACMPU)
682 cmpu.From.Reg = v.Args[0].Reg()
683 cmpu.From.Type = obj.TYPE_REG
684 cmpu.To.Reg = v.Args[1].Reg()
685 cmpu.To.Type = obj.TYPE_RE
    [all...]
  /external/llvm/test/MC/Mips/dspr2/
valid.s 36 cmpu.eq.qb $20, $21 # CHECK: cmpu.eq.qb $20, $21 # encoding: [0x7e,0x95,0x00,0x11]
37 cmpu.lt.qb $22, $23 # CHECK: cmpu.lt.qb $22, $23 # encoding: [0x7e,0xd7,0x00,0x51]
38 cmpu.le.qb $24, $25 # CHECK: cmpu.le.qb $24, $25 # encoding: [0x7f,0x19,0x00,0x91]
  /toolchain/binutils/binutils-2.25/opcodes/
microblaze-opcm.h 28 add, rsub, addc, rsubc, addk, rsubk, addkc, rsubkc, clz, cmp, cmpu, enumerator in enum:microblaze_instr
  /external/llvm/test/MC/Mips/mips32r2/
invalid-dsp.s 24 cmpu.eq.qb $v0,$24 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
25 cmpu.le.qb $s1,$a1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
26 cmpu.lt.qb $at,$a3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
invalid-dspr2.s 34 cmpu.eq.qb $v0,$24 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
35 cmpu.le.qb $s1,$a1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
36 cmpu.lt.qb $at,$a3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled

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