/external/mesa3d/src/gallium/drivers/freedreno/ir3/ |
ir3_shader.h | 137 * + Let the frag shader determine the position/compmask for the 172 uint8_t compmask; member in struct:ir3_shader_variant::__anon27681 333 if (so->inputs[i].compmask && so->inputs[i].bary) 343 uint8_t compmask; member in struct:ir3_shader_linkage::__anon27685 349 ir3_link_add(struct ir3_shader_linkage *l, uint8_t regid, uint8_t compmask, uint8_t loc) 356 l->var[i].compmask = compmask; 358 l->max_loc = MAX2(l->max_loc, loc + util_last_bit(compmask)); 380 fs->inputs[j].compmask, fs->inputs[j].inloc);
|
ir3_shader.c | 77 if (v->inputs[i].compmask) { 394 so->inputs[i].compmask, 415 so->inputs[i].compmask,
|
ir3_compiler_nir.c | 1148 so->inputs[n].compmask = 1; 2504 unsigned j, regid = ~0, compmask = 0, maxcomp = 0; local [all...] |
/external/mesa3d/src/gallium/drivers/freedreno/a3xx/ |
fd3_program.c | 287 reg |= A3XX_SP_VS_OUT_REG_A_COMPMASK(l.var[j].compmask); 291 reg |= A3XX_SP_VS_OUT_REG_B_COMPMASK(l.var[j].compmask); 388 /* NOTE: varyings are packed, so if compmask is 0xb 392 unsigned compmask = fp->inputs[j].compmask; local 401 if (compmask & (1 << i)) { 425 if (compmask & 0x1) { 429 if (compmask & 0x2) { 433 if (compmask & 0x4) { 438 if (compmask & 0x8) [all...] |
fd3_emit.c | 373 if (!vp->inputs[i].compmask) 400 if (vp->inputs[i].compmask) { 427 A3XX_VFD_DECODE_INSTR_WRITEMASK(vp->inputs[i].compmask) | [all...] |
/external/mesa3d/src/gallium/drivers/freedreno/a5xx/ |
fd5_program.c | 150 unsigned compmask = local 169 ir3_link_add(l, v->outputs[k].regid, compmask, nextloc); 174 if (compmask & ~l->var[idx].compmask) { 175 l->var[idx].compmask |= compmask; 177 l->var[idx].loc + util_last_bit(l->var[idx].compmask)); 466 for (j = 0; j < util_last_bit(l.var[i].compmask); j++) 501 reg |= A5XX_SP_VS_OUT_REG_A_COMPMASK(l.var[j].compmask); 505 reg |= A5XX_SP_VS_OUT_REG_B_COMPMASK(l.var[j].compmask); 646 unsigned compmask = s[FS].v->inputs[j].compmask; local [all...] |
fd5_emit.c | 362 if (vp->inputs[i].compmask) { 388 OUT_RING(ring, A5XX_VFD_DEST_CNTL_INSTR_WRITEMASK(vp->inputs[i].compmask) |
|
/external/mesa3d/src/gallium/drivers/freedreno/a4xx/ |
fd4_program.c | 354 reg |= A4XX_SP_VS_OUT_REG_A_COMPMASK(l.var[j].compmask); 358 reg |= A4XX_SP_VS_OUT_REG_B_COMPMASK(l.var[j].compmask); 501 /* NOTE: varyings are packed, so if compmask is 0xb 505 unsigned compmask = s[FS].v->inputs[j].compmask; local 514 if (compmask & (1 << i)) { 538 if (compmask & 0x1) { 542 if (compmask & 0x2) { 546 if (compmask & 0x4) { 551 if (compmask & 0x8) [all...] |
fd4_emit.c | 380 if (!vp->inputs[i].compmask) 407 if (vp->inputs[i].compmask) { 435 A4XX_VFD_DECODE_INSTR_WRITEMASK(vp->inputs[i].compmask) |
|