| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/mips/ |
| mips64r2.s | 56 drotrv $25, $10, $4 # drorv
|
| micromips.s | [all...] |
| /external/llvm/test/MC/Mips/mips5/ |
| invalid-mips64r2.s | 18 drotrv $1,$14,$15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/llvm/test/MC/Mips/mips64/ |
| invalid-mips64r2.s | 19 drotrv $1,$14,$15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/llvm/test/MC/Mips/ |
| rotations64.s | 95 # CHECK-64R: drotrv $4, $4, $1 # encoding: [0x00,0x24,0x20,0x56]
102 # CHECK-64R: drotrv $4, $5, $4 # encoding: [0x00,0x85,0x20,0x56]
171 # CHECK-64R: drotrv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x56]
177 # CHECK-64R: drotrv $4, $5, $6 # encoding: [0x00,0xc5,0x20,0x56]
|
| /external/llvm/test/MC/Mips/mips64r2/ |
| valid.s | 100 drotrv $1,$14,$15 # CHECK: drotrv $1, $14, $15 # encoding: [0x01,0xee,0x08,0x56]
|
| /external/llvm/test/MC/Mips/mips64r3/ |
| valid.s | 100 drotrv $1,$14,$15 # CHECK: drotrv $1, $14, $15 # encoding: [0x01,0xee,0x08,0x56]
|
| /external/llvm/test/MC/Mips/mips64r5/ |
| valid.s | 100 drotrv $1,$14,$15 # CHECK: drotrv $1, $14, $15 # encoding: [0x01,0xee,0x08,0x56]
|
| /external/llvm/test/MC/Mips/micromips64r6/ |
| valid.s | 302 drotrv $3, $6, $4 # CHECK: drotrv $3, $6, $4 # encoding: [0x58,0xc4,0x18,0xd0]
|
| /external/v8/src/mips64/ |
| assembler-mips64.h | 798 void drotrv(Register rd, Register rt, Register rs);
[all...] |
| assembler-mips64.cc | 1889 void Assembler::drotrv(Register rd, Register rt, Register rs) { function in class:v8::internal::Assembler
[all...] |
| macro-assembler-mips64.cc | 1133 drotrv(rd, rs, rt.rm());
[all...] |
| /toolchain/binutils/binutils-2.25/opcodes/ |
| mips-opc.c | [all...] |
