/toolchain/binutils/binutils-2.25/gas/testsuite/gas/mips/ |
mul-ilocks.d | 69 0+00e8 <[^>]*> dsra32 a0,a0,0x1f
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mul.d | 79 0+0128 <[^>]*> dsra32 a0,a0,0x1f
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/external/llvm/test/MC/Mips/mips1/ |
invalid-mips3.s | 41 dsra32 $gp,10 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled 42 dsra32 $gp,$s2,10 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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invalid-mips4.s | 37 dsra32 $gp,$s2,10 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled 38 dsra32 $gp,10 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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invalid-mips5.s | 36 dsra32 $gp,10 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled 37 dsra32 $gp,$s2,10 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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/external/llvm/test/MC/Mips/mips2/ |
invalid-mips3.s | 37 dsra32 $gp,10 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled 38 dsra32 $gp,$s2,10 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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invalid-mips4.s | 35 dsra32 $gp,$s2,10 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled 36 dsra32 $gp,10 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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invalid-mips5.s | 34 dsra32 $gp,10 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled 35 dsra32 $gp,$s2,10 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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/external/llvm/test/MC/Mips/mips3/ |
valid.s | 92 dsra32 $gp,10 # CHECK: dsra32 $gp, $gp, 10 # encoding: [0x00,0x1c,0xe2,0xbf] 93 dsra32 $gp,$s2,10 # CHECK: dsra32 $gp, $18, 10 # encoding: [0x00,0x12,0xe2,0xbf]
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/external/llvm/test/MC/Mips/mips4/ |
valid.s | 96 dsra32 $gp,10 # CHECK: dsra32 $gp, $gp, 10 # encoding: [0x00,0x1c,0xe2,0xbf] 97 dsra32 $gp,$s2,10 # CHECK: dsra32 $gp, $18, 10 # encoding: [0x00,0x12,0xe2,0xbf]
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/external/llvm/test/MC/Mips/mips5/ |
valid.s | 96 dsra32 $gp,10 # CHECK: dsra32 $gp, $gp, 10 # encoding: [0x00,0x1c,0xe2,0xbf] 97 dsra32 $gp,$s2,10 # CHECK: dsra32 $gp, $18, 10 # encoding: [0x00,0x12,0xe2,0xbf]
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/external/llvm/test/MC/Mips/mips64/ |
valid.s | 103 dsra32 $gp,10 # CHECK: dsra32 $gp, $gp, 10 # encoding: [0x00,0x1c,0xe2,0xbf] 104 dsra32 $gp,$s2,10 # CHECK: dsra32 $gp, $18, 10 # encoding: [0x00,0x12,0xe2,0xbf]
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/external/llvm/test/MC/Mips/mips64r2/ |
valid.s | 112 dsra32 $gp,10 # CHECK: dsra32 $gp, $gp, 10 # encoding: [0x00,0x1c,0xe2,0xbf] 113 dsra32 $gp,$s2,10 # CHECK: dsra32 $gp, $18, 10 # encoding: [0x00,0x12,0xe2,0xbf]
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/external/llvm/test/MC/Mips/mips64r3/ |
valid.s | 112 dsra32 $gp,10 # CHECK: dsra32 $gp, $gp, 10 # encoding: [0x00,0x1c,0xe2,0xbf] 113 dsra32 $gp,$s2,10 # CHECK: dsra32 $gp, $18, 10 # encoding: [0x00,0x12,0xe2,0xbf]
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/external/llvm/test/MC/Mips/mips64r5/ |
valid.s | 112 dsra32 $gp,10 # CHECK: dsra32 $gp, $gp, 10 # encoding: [0x00,0x1c,0xe2,0xbf] 113 dsra32 $gp,$s2,10 # CHECK: dsra32 $gp, $18, 10 # encoding: [0x00,0x12,0xe2,0xbf]
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/external/llvm/test/MC/Mips/micromips64r6/ |
invalid.s | 253 dsra32 $4, $5, 32 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected 5-bit unsigned immediate 254 dsra32 $4, $5, -1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected 5-bit unsigned immediate
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valid.s | 278 dsra32 $4, $5, 5 # CHECK: dsra32 $4, $5, 5 # encoding: [0x58,0x85,0x28,0x84]
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/external/v8/src/crankshaft/mips64/ |
lithium-codegen-mips64.cc | [all...] |
/external/v8/src/mips64/ |
codegen-mips64.cc | 636 __ dsra32(at, result, 0);
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assembler-mips64.h | 803 void dsra32(Register rt, Register rd, uint16_t sa); [all...] |
macro-assembler-mips64.cc | [all...] |
macro-assembler-mips64.h | [all...] |
assembler-mips64.cc | 1917 void Assembler::dsra32(Register rd, Register rt, uint16_t sa) { function in class:v8::internal::Assembler [all...] |
/external/v8/src/compiler/mips64/ |
code-generator-mips64.cc | [all...] |
/external/v8/src/full-codegen/mips64/ |
full-codegen-mips64.cc | [all...] |