| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/mips/ |
| rol64.d | 18 0+0024 <[^>]*> dsrl32 a0,a0,0x1f
22 0+0034 <[^>]*> dsrl32 a0,a1,0x1f
25 0+0040 <[^>]*> dsrl32 a0,a1,0x1
28 0+004c <[^>]*> dsrl32 a0,a1,0x0
55 0+00b8 <[^>]*> dsrl32 at,a1,0x0
58 0+00c4 <[^>]*> dsrl32 at,a1,0x1
61 0+00d0 <[^>]*> dsrl32 at,a1,0x1f
66 0+00e4 <[^>]*> dsrl32 a0,a1,0x1f
69 0+00f0 <[^>]*> dsrl32 a0,a1,0x1
72 0+00fc <[^>]*> dsrl32 a0,a1,0x
[all...] |
| dli.d | 22 0+0030 <[^>]*> dsrl32 a0,a0,0x0
24 0+0038 <[^>]*> dsrl32 a0,a0,0x0
81 0+011c <[^>]*> dsrl32 a0,a0,0x0
|
| micromips@dli.d | 23 [0-9a-f]+ <[^>]*> 5884 0048 dsrl32 a0,a0,0x0
25 [0-9a-f]+ <[^>]*> 5884 0048 dsrl32 a0,a0,0x0
82 [0-9a-f]+ <[^>]*> 5884 0048 dsrl32 a0,a0,0x0
|
| /art/runtime/interpreter/mterp/mips64/ |
| op_iput_wide_quick.S | 11 dsrl32 a0, a0, 0
|
| op_aput_wide.S | 19 dsrl32 a2, a2, 0
|
| /external/llvm/test/MC/Mips/ |
| rotations64.s | 106 # CHECK-64: dsrl32 $4, $4, 31 # encoding: [0x00,0x04,0x27,0xfe]
114 # CHECK-64: dsrl32 $4, $5, 31 # encoding: [0x00,0x05,0x27,0xfe]
119 # CHECK-64: dsrl32 $4, $5, 1 # encoding: [0x00,0x05,0x20,0x7e]
124 # CHECK-64: dsrl32 $4, $5, 0 # encoding: [0x00,0x05,0x20,0x3e]
142 # CHECK-64: dsrl32 $4, $5, 31 # encoding: [0x00,0x05,0x27,0xfe]
147 # CHECK-64: dsrl32 $4, $5, 1 # encoding: [0x00,0x05,0x20,0x7e]
152 # CHECK-64: dsrl32 $4, $5, 0 # encoding: [0x00,0x05,0x20,0x3e]
197 # CHECK-64: dsrl32 $1, $5, 0 # encoding: [0x00,0x05,0x08,0x3e]
202 # CHECK-64: dsrl32 $1, $5, 1 # encoding: [0x00,0x05,0x08,0x7e]
207 # CHECK-64: dsrl32 $1, $5, 31 # encoding: [0x00,0x05,0x0f,0xfe
[all...] |
| macro-dla.s | 21 # CHECK: dsrl32 $5, $5, 0 # encoding: [0x00,0x05,0x28,0x3e]
[all...] |
| /external/llvm/test/MC/Mips/mips1/ |
| invalid-mips3.s | 47 dsrl32 $s3,23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
48 dsrl32 $s3,$6,23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| invalid-mips4.s | 43 dsrl32 $s3,$6,23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
44 dsrl32 $s3,23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| invalid-mips5.s | 42 dsrl32 $s3,23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
43 dsrl32 $s3,$6,23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/llvm/test/MC/Mips/mips2/ |
| invalid-mips3.s | 43 dsrl32 $s3,23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
44 dsrl32 $s3,$6,23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| invalid-mips4.s | 41 dsrl32 $s3,$6,23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
42 dsrl32 $s3,23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| invalid-mips5.s | 40 dsrl32 $s3,23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
41 dsrl32 $s3,$6,23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/llvm/test/MC/Mips/mips3/ |
| valid.s | 98 dsrl32 $s3,23 # CHECK: dsrl32 $19, $19, 23 # encoding: [0x00,0x13,0x9d,0xfe]
99 dsrl32 $s3,$6,23 # CHECK: dsrl32 $19, $6, 23 # encoding: [0x00,0x06,0x9d,0xfe]
|
| /external/llvm/test/MC/Mips/mips4/ |
| valid.s | 102 dsrl32 $s3,23 # CHECK: dsrl32 $19, $19, 23 # encoding: [0x00,0x13,0x9d,0xfe]
103 dsrl32 $s3,$6,23 # CHECK: dsrl32 $19, $6, 23 # encoding: [0x00,0x06,0x9d,0xfe]
|
| /external/llvm/test/MC/Mips/mips5/ |
| valid.s | 102 dsrl32 $s3,23 # CHECK: dsrl32 $19, $19, 23 # encoding: [0x00,0x13,0x9d,0xfe]
103 dsrl32 $s3,$6,23 # CHECK: dsrl32 $19, $6, 23 # encoding: [0x00,0x06,0x9d,0xfe]
|
| /external/llvm/test/MC/Mips/mips64/ |
| valid.s | 109 dsrl32 $s3,23 # CHECK: dsrl32 $19, $19, 23 # encoding: [0x00,0x13,0x9d,0xfe]
110 dsrl32 $s3,$6,23 # CHECK: dsrl32 $19, $6, 23 # encoding: [0x00,0x06,0x9d,0xfe]
|
| /external/llvm/test/MC/Mips/mips64r2/ |
| valid.s | 118 dsrl32 $s3,23 # CHECK: dsrl32 $19, $19, 23 # encoding: [0x00,0x13,0x9d,0xfe]
119 dsrl32 $s3,$6,23 # CHECK: dsrl32 $19, $6, 23 # encoding: [0x00,0x06,0x9d,0xfe]
|
| /external/llvm/test/MC/Mips/mips64r3/ |
| valid.s | 118 dsrl32 $s3,23 # CHECK: dsrl32 $19, $19, 23 # encoding: [0x00,0x13,0x9d,0xfe]
119 dsrl32 $s3,$6,23 # CHECK: dsrl32 $19, $6, 23 # encoding: [0x00,0x06,0x9d,0xfe]
|
| /external/llvm/test/MC/Mips/mips64r5/ |
| valid.s | 118 dsrl32 $s3,23 # CHECK: dsrl32 $19, $19, 23 # encoding: [0x00,0x13,0x9d,0xfe]
119 dsrl32 $s3,$6,23 # CHECK: dsrl32 $19, $6, 23 # encoding: [0x00,0x06,0x9d,0xfe]
|
| /external/llvm/test/MC/Mips/micromips64r6/ |
| valid.s | 308 dsrl32 $3, $4, 5 # CHECK: dsrl32 $3, $4, 5 # encoding: [0x58,0x64,0x28,0x48]
|
| /external/v8/src/compiler/mips64/ |
| code-generator-mips64.cc | [all...] |
| /external/v8/src/mips64/ |
| assembler-mips64.h | 802 void dsrl32(Register rt, Register rd, uint16_t sa);
[all...] |
| macro-assembler-mips64.cc | 1241 dsrl32(src, src, 0);
[all...] |
| /external/v8/src/crankshaft/mips64/ |
| lithium-codegen-mips64.cc | [all...] |
