| /external/mesa3d/src/gallium/drivers/radeon/ |
| r600_streamout.c | 80 unsigned num_bufs = util_bitcount(rctx->streamout.enabled_mask);
81 unsigned num_bufs_appended = util_bitcount(rctx->streamout.enabled_mask &
119 unsigned enabled_mask = 0, append_bitmask = 0; local
133 enabled_mask |= 1 << i;
141 rctx->streamout.enabled_mask = enabled_mask;
345 rctx->streamout.hw_enabled_mask = rctx->streamout.enabled_mask |
346 (rctx->streamout.enabled_mask << 4) |
347 (rctx->streamout.enabled_mask << 8) |
348 (rctx->streamout.enabled_mask << 12)
[all...] |
| r600_pipe_common.h | 471 unsigned enabled_mask; member in struct:r600_streamout
[all...] |
| /external/mesa3d/src/gallium/drivers/virgl/ |
| virgl_context.h | 48 uint32_t enabled_mask; member in struct:virgl_textures_info
|
| virgl_context.c | 107 uint32_t remaining_mask = tinfo->enabled_mask;
705 remaining_mask = tinfo->enabled_mask & disable_mask;
729 tinfo->enabled_mask &= ~disable_mask;
730 tinfo->enabled_mask |= new_mask;
[all...] |
| /external/mesa3d/src/gallium/drivers/radeonsi/ |
| si_descriptors.c | 343 unsigned mask = views->enabled_mask;
469 views->enabled_mask |= 1u << slot;
471 /* Since this can flush, it must be done after enabled_mask is
486 views->enabled_mask &= ~(1u << slot);
569 unsigned mask = samplers->views.enabled_mask;
617 uint mask = images->enabled_mask;
636 if (images->enabled_mask & (1u << slot)) {
643 images->enabled_mask &= ~(1u << slot);
753 images->enabled_mask |= 1u << slot;
757 /* Since this can flush, it must be done after enabled_mask is updated. *
[all...] |
| si_state.h | 248 unsigned enabled_mask; member in struct:si_sampler_views
257 unsigned enabled_mask; member in struct:si_buffer_resources
|
| si_pipe.h | 162 unsigned enabled_mask; member in struct:si_images_info
|
| si_blit.c | 530 uint32_t mask = textures->views.enabled_mask;
571 uint32_t mask = images->enabled_mask;
[all...] |
| /external/mesa3d/src/gallium/drivers/freedreno/a2xx/ |
| fd2_emit.c | 57 uint32_t enabled_mask = constbuf->enabled_mask; local
63 constbuf->dirty_mask = enabled_mask;
66 while (enabled_mask) {
67 unsigned index = ffs(enabled_mask) - 1;
103 enabled_mask &= ~(1 << index);
|
| /external/mesa3d/src/gallium/drivers/etnaviv/ |
| etnaviv_context.h | 79 uint32_t enabled_mask; member in struct:etna_vertexbuf_state
|
| etnaviv_state.c | 417 util_set_vertex_buffers_mask(so->vb, &so->enabled_mask, vb, start_slot, num_buffers);
418 so->count = util_last_bit(so->enabled_mask);
|
| /external/mesa3d/src/gallium/drivers/freedreno/ |
| freedreno_state.c | 104 so->enabled_mask &= ~(1 << index);
109 so->enabled_mask |= 1 << index;
223 util_set_vertex_buffers_mask(so->vb, &so->enabled_mask, vb, start_slot, count);
224 so->count = util_last_bit(so->enabled_mask);
|
| freedreno_context.h | 71 uint32_t enabled_mask; member in struct:fd_constbuf_stateobj
78 uint32_t enabled_mask; member in struct:fd_vertexbuf_stateobj
|
| freedreno_draw.c | 139 foreach_bit(i, ctx->constbuf[PIPE_SHADER_VERTEX].enabled_mask)
141 foreach_bit(i, ctx->constbuf[PIPE_SHADER_FRAGMENT].enabled_mask)
145 foreach_bit(i, ctx->vtx.vertexbuf.enabled_mask) {
|
| /external/mesa3d/src/gallium/drivers/ilo/ |
| ilo_state.h | 163 uint32_t enabled_mask; member in struct:ilo_vb_state
201 uint32_t enabled_mask; member in struct:ilo_cbuf_state
|
| ilo_state.c | 365 uint32_t upload_mask = cbuf->enabled_mask;
[all...] |
| ilo_shader.c | 247 if ((vec->cbuf[info->type].enabled_mask & 0x1) &&
[all...] |
| /external/mesa3d/src/gallium/drivers/vc4/ |
| vc4_context.h | 193 uint32_t enabled_mask; member in struct:vc4_constbuf_stateobj
200 uint32_t enabled_mask; member in struct:vc4_vertexbuf_stateobj
|
| vc4_state.c | 297 util_set_vertex_buffers_mask(so->vb, &so->enabled_mask, vb,
299 so->count = util_last_bit(so->enabled_mask);
389 so->enabled_mask &= ~(1 << index);
399 so->enabled_mask |= 1 << index;
|
| /external/mesa3d/src/gallium/drivers/r600/ |
| r600_hw_context.c | 350 ctx->vertex_buffer_state.dirty_mask = ctx->vertex_buffer_state.enabled_mask;
358 constbuf->dirty_mask = constbuf->enabled_mask;
359 samplers->views.dirty_mask = samplers->views.enabled_mask;
360 samplers->states.dirty_mask = samplers->states.enabled_mask;
|
| r600_state_common.c | 456 dst->states.enabled_mask &= ~disable_mask;
457 dst->states.dirty_mask &= dst->states.enabled_mask;
458 dst->states.enabled_mask |= new_mask;
460 dst->states.has_bordercolor_mask &= dst->states.enabled_mask;
582 rctx->vertex_buffer_state.enabled_mask &= ~disable_mask;
583 rctx->vertex_buffer_state.dirty_mask &= rctx->vertex_buffer_state.enabled_mask;
584 rctx->vertex_buffer_state.enabled_mask |= new_buffer_mask;
625 remaining_mask = dst->views.enabled_mask & disable_mask;
660 (dst->states.enabled_mask & (1 << i)) &&
675 dst->views.enabled_mask &= ~disable_mask
[all...] |
| r600_pipe.h | 352 uint32_t enabled_mask; member in struct:r600_samplerview_state
362 uint32_t enabled_mask; member in struct:r600_sampler_states
386 uint32_t enabled_mask; member in struct:r600_constbuf_state
394 uint32_t enabled_mask; /* non-NULL buffers */ member in struct:r600_vertexbuf_state
|
| r600_blit.c | 82 rctx->blitter, util_last_bit(rctx->samplers[PIPE_SHADER_FRAGMENT].states.enabled_mask),
86 rctx->blitter, util_last_bit(rctx->samplers[PIPE_SHADER_FRAGMENT].views.enabled_mask),
|
| evergreen_compute.c | 155 state->enabled_mask |= 1 << vb_index;
[all...] |
| /external/mesa3d/src/gallium/drivers/freedreno/ir3/ |
| ir3_shader.c | 494 uint32_t dirty_mask = constbuf->enabled_mask;
541 if ((constbuf->enabled_mask & (1 << index)) && cb->buffer) {
|
