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  /external/clang/test/Sema/
default.c 3 void f5 (int z) { function
  /external/clang/test/ASTMerge/Inputs/
function1.c 6 int f5(int) __attribute__((const));
function2.c 7 int f5(int) __attribute__((const));
  /toolchain/binutils/binutils-2.25/gas/testsuite/gas/ia64/
opc-f.s 5 fma f4 = f5, f6, f7
6 fma.s0 f4 = f5, f6, f7
7 fma.s1 f4 = f5, f6, f7
8 fma.s2 f4 = f5, f6, f7
9 fma.s3 f4 = f5, f6, f7
11 fma.s f4 = f5, f6, f7
12 fma.s.s0 f4 = f5, f6, f7
13 fma.s.s1 f4 = f5, f6, f7
14 fma.s.s2 f4 = f5, f6, f7
15 fma.s.s3 f4 = f5, f6, f
    [all...]
  /external/clang/test/CodeGen/
inline2.c 24 // CHECK-GNU89-LABEL: define i32 @f5()
25 // CHECK-C99-LABEL: define i32 @f5()
26 extern inline int f5(void);
27 inline int f5(void) { return 0; } function
65 return f0() + f1() + f2() + f3() + f4() + f5() + f6() + f7() + f8() + f9()
microsoft-call-conv-x64.c 10 void __stdcall f5(void) { function
11 // CHECK-LABEL: define void @f5()
20 void (__stdcall *pf5)(void) = f5;
23 f4(); f5();
25 // CHECK: call void @f5()
x86_64-arguments-win32.c 21 // CHECK-LABEL: define void @f5(i64 %a.coerce)
22 void f5(_Complex float a) {} function
struct-passing.c 15 void __attribute__((pure)) f5(T1 a);
17 void *ps[] = { f0, f1, f2, f3, f4, f5 };
24 // CHECK: declare void @f5({{.*}} byval align 4)
  /external/clang/test/CoverageMapping/
unused_function.cpp 28 // CHECK: {{_Z2f5v|\?f5@@YAXXZ}}:
30 inline void f5() {
  /toolchain/binutils/binutils-2.25/gas/testsuite/gas/mips/
l_d-reloc.d 8 [0-9a-f]+ <[^>]*> lwc1 \$f5,0\(\$5\)
10 [0-9a-f]+ <[^>]*> lwc1 \$f5,32763\(\$5\)
13 [0-9a-f]+ <[^>]*> lwc1 \$f5,0\(\$1\)
16 [0-9a-f]+ <[^>]*> lwc1 \$f5,0\(\$1\)
20 [0-9a-f]+ <[^>]*> lwc1 \$f5,-32768\(\$1\)
24 [0-9a-f]+ <[^>]*> lwc1 \$f5,32763\(\$1\)
29 [0-9a-f]+ <[^>]*> lwc1 \$f5,0\(\$1\)
34 [0-9a-f]+ <[^>]*> lwc1 \$f5,0\(\$1\)
38 [0-9a-f]+ <[^>]*> lwc1 \$f5,-32768\(\$1\)
43 [0-9a-f]+ <[^>]*> lwc1 \$f5,0\(\$1\
    [all...]
  /external/clang/test/CodeGenCXX/
friend-redecl.cpp 14 bool TryFoo(Foo *f5);
reinterpret-cast.cpp 17 void f5(void*& u) { function
  /external/clang/test/Parser/
cxx-stmt.cpp 57 void f5() { function
66 return f5(), // ok
  /toolchain/binutils/binutils-2.25/ld/testsuite/ld-xtensa/
diff_overflow2.s 15 f5: label
22 .byte .Lf5 - f5
  /toolchain/binutils/binutils-2.25/gas/testsuite/gas/arm/
float.s 5 mvfeqe f3, f5
14 adfsm f3, f4, f5
18 sufneez f3, f4, f5
30 dvfmism f3, f4, f5
49 fmleqs f1, f3, f5
58 frdgtsz f4, f4, f5
62 poleqe f5, f6, f7
67 mnfeqez f0, f5
73 abseqe f4, f5
79 sqts f5, f
    [all...]
  /toolchain/binutils/binutils-2.25/gas/testsuite/gas/i386/
avx512er-rcigrd-intel.d 12 [ ]*[a-f0-9]+:[ ]*62 f2 7d 38 c8 f5[ ]*vexp2ps zmm6,zmm5,\{sae\}
13 [ ]*[a-f0-9]+:[ ]*62 f2 fd 38 c8 f5[ ]*vexp2pd zmm6,zmm5,\{sae\}
14 [ ]*[a-f0-9]+:[ ]*62 f2 7d 38 ca f5[ ]*vrcp28ps zmm6,zmm5,\{sae\}
15 [ ]*[a-f0-9]+:[ ]*62 f2 fd 38 ca f5[ ]*vrcp28pd zmm6,zmm5,\{sae\}
18 [ ]*[a-f0-9]+:[ ]*62 f2 7d 38 cc f5[ ]*vrsqrt28ps zmm6,zmm5,\{sae\}
19 [ ]*[a-f0-9]+:[ ]*62 f2 fd 38 cc f5[ ]*vrsqrt28pd zmm6,zmm5,\{sae\}
22 [ ]*[a-f0-9]+:[ ]*62 f2 7d 38 c8 f5[ ]*vexp2ps zmm6,zmm5,\{sae\}
23 [ ]*[a-f0-9]+:[ ]*62 f2 fd 38 c8 f5[ ]*vexp2pd zmm6,zmm5,\{sae\}
24 [ ]*[a-f0-9]+:[ ]*62 f2 7d 38 ca f5[ ]*vrcp28ps zmm6,zmm5,\{sae\}
25 [ ]*[a-f0-9]+:[ ]*62 f2 fd 38 ca f5[ ]*vrcp28pd zmm6,zmm5,\{sae\
    [all...]
avx512er-rcigrd.d 12 [ ]*[a-f0-9]+:[ ]*62 f2 7d 38 c8 f5[ ]*vexp2ps \{sae\},%zmm5,%zmm6
13 [ ]*[a-f0-9]+:[ ]*62 f2 fd 38 c8 f5[ ]*vexp2pd \{sae\},%zmm5,%zmm6
14 [ ]*[a-f0-9]+:[ ]*62 f2 7d 38 ca f5[ ]*vrcp28ps \{sae\},%zmm5,%zmm6
15 [ ]*[a-f0-9]+:[ ]*62 f2 fd 38 ca f5[ ]*vrcp28pd \{sae\},%zmm5,%zmm6
18 [ ]*[a-f0-9]+:[ ]*62 f2 7d 38 cc f5[ ]*vrsqrt28ps \{sae\},%zmm5,%zmm6
19 [ ]*[a-f0-9]+:[ ]*62 f2 fd 38 cc f5[ ]*vrsqrt28pd \{sae\},%zmm5,%zmm6
22 [ ]*[a-f0-9]+:[ ]*62 f2 7d 38 c8 f5[ ]*vexp2ps \{sae\},%zmm5,%zmm6
23 [ ]*[a-f0-9]+:[ ]*62 f2 fd 38 c8 f5[ ]*vexp2pd \{sae\},%zmm5,%zmm6
24 [ ]*[a-f0-9]+:[ ]*62 f2 7d 38 ca f5[ ]*vrcp28ps \{sae\},%zmm5,%zmm6
25 [ ]*[a-f0-9]+:[ ]*62 f2 fd 38 ca f5[ ]*vrcp28pd \{sae\},%zmm5,%zmm
    [all...]
avx512er-rcigrne-intel.d 12 [ ]*[a-f0-9]+:[ ]*62 f2 7d 18 c8 f5[ ]*vexp2ps zmm6,zmm5,\{sae\}
13 [ ]*[a-f0-9]+:[ ]*62 f2 fd 18 c8 f5[ ]*vexp2pd zmm6,zmm5,\{sae\}
14 [ ]*[a-f0-9]+:[ ]*62 f2 7d 18 ca f5[ ]*vrcp28ps zmm6,zmm5,\{sae\}
15 [ ]*[a-f0-9]+:[ ]*62 f2 fd 18 ca f5[ ]*vrcp28pd zmm6,zmm5,\{sae\}
18 [ ]*[a-f0-9]+:[ ]*62 f2 7d 18 cc f5[ ]*vrsqrt28ps zmm6,zmm5,\{sae\}
19 [ ]*[a-f0-9]+:[ ]*62 f2 fd 18 cc f5[ ]*vrsqrt28pd zmm6,zmm5,\{sae\}
22 [ ]*[a-f0-9]+:[ ]*62 f2 7d 18 c8 f5[ ]*vexp2ps zmm6,zmm5,\{sae\}
23 [ ]*[a-f0-9]+:[ ]*62 f2 fd 18 c8 f5[ ]*vexp2pd zmm6,zmm5,\{sae\}
24 [ ]*[a-f0-9]+:[ ]*62 f2 7d 18 ca f5[ ]*vrcp28ps zmm6,zmm5,\{sae\}
25 [ ]*[a-f0-9]+:[ ]*62 f2 fd 18 ca f5[ ]*vrcp28pd zmm6,zmm5,\{sae\
    [all...]
avx512er-rcigrne.d 12 [ ]*[a-f0-9]+:[ ]*62 f2 7d 18 c8 f5[ ]*vexp2ps \{sae\},%zmm5,%zmm6
13 [ ]*[a-f0-9]+:[ ]*62 f2 fd 18 c8 f5[ ]*vexp2pd \{sae\},%zmm5,%zmm6
14 [ ]*[a-f0-9]+:[ ]*62 f2 7d 18 ca f5[ ]*vrcp28ps \{sae\},%zmm5,%zmm6
15 [ ]*[a-f0-9]+:[ ]*62 f2 fd 18 ca f5[ ]*vrcp28pd \{sae\},%zmm5,%zmm6
18 [ ]*[a-f0-9]+:[ ]*62 f2 7d 18 cc f5[ ]*vrsqrt28ps \{sae\},%zmm5,%zmm6
19 [ ]*[a-f0-9]+:[ ]*62 f2 fd 18 cc f5[ ]*vrsqrt28pd \{sae\},%zmm5,%zmm6
22 [ ]*[a-f0-9]+:[ ]*62 f2 7d 18 c8 f5[ ]*vexp2ps \{sae\},%zmm5,%zmm6
23 [ ]*[a-f0-9]+:[ ]*62 f2 fd 18 c8 f5[ ]*vexp2pd \{sae\},%zmm5,%zmm6
24 [ ]*[a-f0-9]+:[ ]*62 f2 7d 18 ca f5[ ]*vrcp28ps \{sae\},%zmm5,%zmm6
25 [ ]*[a-f0-9]+:[ ]*62 f2 fd 18 ca f5[ ]*vrcp28pd \{sae\},%zmm5,%zmm
    [all...]
avx512er-rcigru-intel.d 12 [ ]*[a-f0-9]+:[ ]*62 f2 7d 58 c8 f5[ ]*vexp2ps zmm6,zmm5,\{sae\}
13 [ ]*[a-f0-9]+:[ ]*62 f2 fd 58 c8 f5[ ]*vexp2pd zmm6,zmm5,\{sae\}
14 [ ]*[a-f0-9]+:[ ]*62 f2 7d 58 ca f5[ ]*vrcp28ps zmm6,zmm5,\{sae\}
15 [ ]*[a-f0-9]+:[ ]*62 f2 fd 58 ca f5[ ]*vrcp28pd zmm6,zmm5,\{sae\}
18 [ ]*[a-f0-9]+:[ ]*62 f2 7d 58 cc f5[ ]*vrsqrt28ps zmm6,zmm5,\{sae\}
19 [ ]*[a-f0-9]+:[ ]*62 f2 fd 58 cc f5[ ]*vrsqrt28pd zmm6,zmm5,\{sae\}
22 [ ]*[a-f0-9]+:[ ]*62 f2 7d 58 c8 f5[ ]*vexp2ps zmm6,zmm5,\{sae\}
23 [ ]*[a-f0-9]+:[ ]*62 f2 fd 58 c8 f5[ ]*vexp2pd zmm6,zmm5,\{sae\}
24 [ ]*[a-f0-9]+:[ ]*62 f2 7d 58 ca f5[ ]*vrcp28ps zmm6,zmm5,\{sae\}
25 [ ]*[a-f0-9]+:[ ]*62 f2 fd 58 ca f5[ ]*vrcp28pd zmm6,zmm5,\{sae\
    [all...]
avx512er-rcigru.d 12 [ ]*[a-f0-9]+:[ ]*62 f2 7d 58 c8 f5[ ]*vexp2ps \{sae\},%zmm5,%zmm6
13 [ ]*[a-f0-9]+:[ ]*62 f2 fd 58 c8 f5[ ]*vexp2pd \{sae\},%zmm5,%zmm6
14 [ ]*[a-f0-9]+:[ ]*62 f2 7d 58 ca f5[ ]*vrcp28ps \{sae\},%zmm5,%zmm6
15 [ ]*[a-f0-9]+:[ ]*62 f2 fd 58 ca f5[ ]*vrcp28pd \{sae\},%zmm5,%zmm6
18 [ ]*[a-f0-9]+:[ ]*62 f2 7d 58 cc f5[ ]*vrsqrt28ps \{sae\},%zmm5,%zmm6
19 [ ]*[a-f0-9]+:[ ]*62 f2 fd 58 cc f5[ ]*vrsqrt28pd \{sae\},%zmm5,%zmm6
22 [ ]*[a-f0-9]+:[ ]*62 f2 7d 58 c8 f5[ ]*vexp2ps \{sae\},%zmm5,%zmm6
23 [ ]*[a-f0-9]+:[ ]*62 f2 fd 58 c8 f5[ ]*vexp2pd \{sae\},%zmm5,%zmm6
24 [ ]*[a-f0-9]+:[ ]*62 f2 7d 58 ca f5[ ]*vrcp28ps \{sae\},%zmm5,%zmm6
25 [ ]*[a-f0-9]+:[ ]*62 f2 fd 58 ca f5[ ]*vrcp28pd \{sae\},%zmm5,%zmm
    [all...]
avx512er-rcigrz-intel.d 12 [ ]*[a-f0-9]+:[ ]*62 f2 7d 78 c8 f5[ ]*vexp2ps zmm6,zmm5,\{sae\}
13 [ ]*[a-f0-9]+:[ ]*62 f2 fd 78 c8 f5[ ]*vexp2pd zmm6,zmm5,\{sae\}
14 [ ]*[a-f0-9]+:[ ]*62 f2 7d 78 ca f5[ ]*vrcp28ps zmm6,zmm5,\{sae\}
15 [ ]*[a-f0-9]+:[ ]*62 f2 fd 78 ca f5[ ]*vrcp28pd zmm6,zmm5,\{sae\}
18 [ ]*[a-f0-9]+:[ ]*62 f2 7d 78 cc f5[ ]*vrsqrt28ps zmm6,zmm5,\{sae\}
19 [ ]*[a-f0-9]+:[ ]*62 f2 fd 78 cc f5[ ]*vrsqrt28pd zmm6,zmm5,\{sae\}
22 [ ]*[a-f0-9]+:[ ]*62 f2 7d 78 c8 f5[ ]*vexp2ps zmm6,zmm5,\{sae\}
23 [ ]*[a-f0-9]+:[ ]*62 f2 fd 78 c8 f5[ ]*vexp2pd zmm6,zmm5,\{sae\}
24 [ ]*[a-f0-9]+:[ ]*62 f2 7d 78 ca f5[ ]*vrcp28ps zmm6,zmm5,\{sae\}
25 [ ]*[a-f0-9]+:[ ]*62 f2 fd 78 ca f5[ ]*vrcp28pd zmm6,zmm5,\{sae\
    [all...]
avx512er-rcigrz.d 12 [ ]*[a-f0-9]+:[ ]*62 f2 7d 78 c8 f5[ ]*vexp2ps \{sae\},%zmm5,%zmm6
13 [ ]*[a-f0-9]+:[ ]*62 f2 fd 78 c8 f5[ ]*vexp2pd \{sae\},%zmm5,%zmm6
14 [ ]*[a-f0-9]+:[ ]*62 f2 7d 78 ca f5[ ]*vrcp28ps \{sae\},%zmm5,%zmm6
15 [ ]*[a-f0-9]+:[ ]*62 f2 fd 78 ca f5[ ]*vrcp28pd \{sae\},%zmm5,%zmm6
18 [ ]*[a-f0-9]+:[ ]*62 f2 7d 78 cc f5[ ]*vrsqrt28ps \{sae\},%zmm5,%zmm6
19 [ ]*[a-f0-9]+:[ ]*62 f2 fd 78 cc f5[ ]*vrsqrt28pd \{sae\},%zmm5,%zmm6
22 [ ]*[a-f0-9]+:[ ]*62 f2 7d 78 c8 f5[ ]*vexp2ps \{sae\},%zmm5,%zmm6
23 [ ]*[a-f0-9]+:[ ]*62 f2 fd 78 c8 f5[ ]*vexp2pd \{sae\},%zmm5,%zmm6
24 [ ]*[a-f0-9]+:[ ]*62 f2 7d 78 ca f5[ ]*vrcp28ps \{sae\},%zmm5,%zmm6
25 [ ]*[a-f0-9]+:[ ]*62 f2 fd 78 ca f5[ ]*vrcp28pd \{sae\},%zmm5,%zmm
    [all...]
x86-64-avx512bw_vl-opts-intel.d 12 [ ]*[a-f0-9]+:[ ]*62 01 7f 08 6f f5[ ]*vmovdqu8 xmm30,xmm29
14 [ ]*[a-f0-9]+:[ ]*62 01 7f 0f 6f f5[ ]*vmovdqu8 xmm30\{k7\},xmm29
16 [ ]*[a-f0-9]+:[ ]*62 01 7f 8f 6f f5[ ]*vmovdqu8 xmm30\{k7\}\{z\},xmm29
18 [ ]*[a-f0-9]+:[ ]*62 01 7f 08 6f f5[ ]*vmovdqu8 xmm30,xmm29
20 [ ]*[a-f0-9]+:[ ]*62 01 7f 0f 6f f5[ ]*vmovdqu8 xmm30\{k7\},xmm29
22 [ ]*[a-f0-9]+:[ ]*62 01 7f 8f 6f f5[ ]*vmovdqu8 xmm30\{k7\}\{z\},xmm29
24 [ ]*[a-f0-9]+:[ ]*62 01 7f 28 6f f5[ ]*vmovdqu8 ymm30,ymm29
26 [ ]*[a-f0-9]+:[ ]*62 01 7f 2f 6f f5[ ]*vmovdqu8 ymm30\{k7\},ymm29
28 [ ]*[a-f0-9]+:[ ]*62 01 7f af 6f f5[ ]*vmovdqu8 ymm30\{k7\}\{z\},ymm29
30 [ ]*[a-f0-9]+:[ ]*62 01 7f 28 6f f5[ ]*vmovdqu8 ymm30,ymm2
    [all...]
x86-64-avx512bw_vl-opts.d 12 [ ]*[a-f0-9]+:[ ]*62 01 7f 08 6f f5[ ]*vmovdqu8 %xmm29,%xmm30
14 [ ]*[a-f0-9]+:[ ]*62 01 7f 0f 6f f5[ ]*vmovdqu8 %xmm29,%xmm30\{%k7\}
16 [ ]*[a-f0-9]+:[ ]*62 01 7f 8f 6f f5[ ]*vmovdqu8 %xmm29,%xmm30\{%k7\}\{z\}
18 [ ]*[a-f0-9]+:[ ]*62 01 7f 08 6f f5[ ]*vmovdqu8 %xmm29,%xmm30
20 [ ]*[a-f0-9]+:[ ]*62 01 7f 0f 6f f5[ ]*vmovdqu8 %xmm29,%xmm30\{%k7\}
22 [ ]*[a-f0-9]+:[ ]*62 01 7f 8f 6f f5[ ]*vmovdqu8 %xmm29,%xmm30\{%k7\}\{z\}
24 [ ]*[a-f0-9]+:[ ]*62 01 7f 28 6f f5[ ]*vmovdqu8 %ymm29,%ymm30
26 [ ]*[a-f0-9]+:[ ]*62 01 7f 2f 6f f5[ ]*vmovdqu8 %ymm29,%ymm30\{%k7\}
28 [ ]*[a-f0-9]+:[ ]*62 01 7f af 6f f5[ ]*vmovdqu8 %ymm29,%ymm30\{%k7\}\{z\}
30 [ ]*[a-f0-9]+:[ ]*62 01 7f 28 6f f5[ ]*vmovdqu8 %ymm29,%ymm3
    [all...]

Completed in 464 milliseconds

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