| /external/clang/test/CodeGen/ |
| inline2.c | 34 // CHECK-GNU89-LABEL: define i32 @f7()
35 // CHECK-C99-LABEL: define i32 @f7()
36 extern inline int f7(void);
37 extern int f7(void) { return 0; } function
65 return f0() + f1() + f2() + f3() + f4() + f5() + f6() + f7() + f8() + f9()
|
| x86_64-arguments-win32.c | 27 // CHECK-LABEL: define i64 @f7()
28 _Complex float f7() { return 1.0; } function
|
| microsoft-call-conv-x64.c | 35 void __stdcall f7(foo) int foo; {} function
37 f7(0);
38 // CHECK: call void @f7(i32 0)
|
| microsoft-call-conv.c | 56 void __stdcall f7(foo) int foo; {} function
58 f7(0);
59 // CHECK: call x86_stdcallcc void @f7(i32 0)
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/mips/ |
| mips32-sf32.s | 8 cvt.d.s $f8,$f7
9 cvt.d.w $f8,$f7
10 cvt.s.d $f7,$f8
11 trunc.w.d $f7,$f8
|
| mips32-sf32.d | 15 0+0010 <[^>]*> 46003a21 cvt.d.s \$f8,\$f7
16 0+0014 <[^>]*> 46803a21 cvt.d.w \$f8,\$f7
17 0+0018 <[^>]*> 462041e0 cvt.s.d \$f7,\$f8
18 0+001c <[^>]*> 462041cd trunc.w.d \$f7,\$f8
|
| micromips@mips32-sf32.d | 16 [0-9a-f]+ <[^>]*> 5507 137b cvt\.d\.s \$f8,\$f7
17 [0-9a-f]+ <[^>]*> 5507 337b cvt\.d\.w \$f8,\$f7
18 [0-9a-f]+ <[^>]*> 54e8 1b7b cvt\.s\.d \$f7,\$f8
19 [0-9a-f]+ <[^>]*> 54e8 6b3b trunc\.w\.d \$f7,\$f8
|
| mips32-sf32.l | 5 .*:8: Error: opcode not supported on this processor: .* \(.*\) `cvt.d.s \$f8,\$f7'
6 .*:9: Error: opcode not supported on this processor: .* \(.*\) `cvt.d.w \$f8,\$f7'
7 .*:10: Error: opcode not supported on this processor: .* \(.*\) `cvt.s.d \$f7,\$f8'
8 .*:11: Error: opcode not supported on this processor: .* \(.*\) `trunc.w.d \$f7,\$f8'
|
| /external/llvm/test/MC/Mips/ |
| mips-fpu-instructions.s | 10 # CHECK: abs.s $f6, $f7 # encoding: [0x85,0x39,0x00,0x46]
12 # CHECK: add.s $f9, $f6, $f7 # encoding: [0x40,0x32,0x07,0x46]
14 # CHECK: floor.w.s $f6, $f7 # encoding: [0x8f,0x39,0x00,0x46]
16 # CHECK: ceil.w.s $f6, $f7 # encoding: [0x8e,0x39,0x00,0x46]
18 # CHECK: mul.s $f9, $f6, $f7 # encoding: [0x42,0x32,0x07,0x46]
20 # CHECK: neg.s $f6, $f7 # encoding: [0x87,0x39,0x00,0x46]
22 # CHECK: round.w.s $f6, $f7 # encoding: [0x8c,0x39,0x00,0x46]
24 # CHECK: sqrt.s $f6, $f7 # encoding: [0x84,0x39,0x00,0x46]
26 # CHECK: sub.s $f9, $f6, $f7 # encoding: [0x41,0x32,0x07,0x46]
28 # CHECK: trunc.w.s $f6, $f7 # encoding: [0x8d,0x39,0x00,0x46
[all...] |
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/arm/ |
| float.s | 7 mvfs f4, f7
10 mvfez f7, f7
22 rsfled f7, f6, f0
33 rdfs f3, f7, #0f1
38 powcsez f4, f7, #1
40 rpws f7, f6, f7
46 rmfep f4, f7, f0
62 poleqe f5, f6, f7
[all...] |
| float.d | 11 0+00c <[^>]+> ee00c107 ? mvfs f4, f7
14 0+018 <[^>]+> ee08f167 ? mvfez f7, f7
23 0+03c <[^>]+> de367180 ? rsfled f7, f6, f0
31 0+05c <[^>]+> ee573109 ? rdfs f3, f7, #1\.0
35 0+06c <[^>]+> 2e6f4169 ? powcsez f4, f7, #1\.0
36 0+070 <[^>]+> ee767107 ? rpws f7, f6, f7
41 0+084 <[^>]+> ee8f4120 ? rmfep f4, f7, f0
53 0+0b4 <[^>]+> 0ece5107 ? poleqe f5, f6, f7
[all...] |
| /external/clang/test/Sema/ |
| warn-unused-function.c | 23 static void f7(void);
25 void f9(void) { f8(f7); }
26 static void f7(void) {} function
|
| MicrosoftCompatibility.c | 23 __declspec(__noreturn__) void f7(void); /* expected-warning {{__declspec attribute '__noreturn__' is not supported}} */
|
| floating-point-compare.c | 23 int f7(float x) { function
|
| /external/clang/test/SemaCXX/ |
| dcl_ambig_res.cpp | 59 void f7(int(C7)) { } // expected-note{{candidate}} function
62 f7(1); // expected-error{{no matching function}}
63 f7(g7); //OK
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/tic54x/ |
| field.d | 25 0+006 <f7>:
|
| field.s | 5 .global f1,f2,f3,f4,f5,f6,f7,f8
12 f7: .field 3,3 label
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/i386/ |
| bmi2-intel.d | 22 [ ]*[a-f0-9]+: c4 e2 7a f7 f3 sarx esi,ebx,eax
23 [ ]*[a-f0-9]+: c4 e2 62 f7 31 sarx esi,DWORD PTR \[ecx\],ebx
24 [ ]*[a-f0-9]+: c4 e2 79 f7 f3 shlx esi,ebx,eax
25 [ ]*[a-f0-9]+: c4 e2 61 f7 31 shlx esi,DWORD PTR \[ecx\],ebx
26 [ ]*[a-f0-9]+: c4 e2 7b f7 f3 shrx esi,ebx,eax
27 [ ]*[a-f0-9]+: c4 e2 63 f7 31 shrx esi,DWORD PTR \[ecx\],ebx
43 [ ]*[a-f0-9]+: c4 e2 7a f7 f3 sarx esi,ebx,eax
44 [ ]*[a-f0-9]+: c4 e2 62 f7 31 sarx esi,DWORD PTR \[ecx\],ebx
45 [ ]*[a-f0-9]+: c4 e2 62 f7 31 sarx esi,DWORD PTR \[ecx\],ebx
46 [ ]*[a-f0-9]+: c4 e2 79 f7 f3 shlx esi,ebx,ea
[all...] |
| bmi2.d | 21 [ ]*[a-f0-9]+: c4 e2 7a f7 f3 sarx %eax,%ebx,%esi
22 [ ]*[a-f0-9]+: c4 e2 62 f7 31 sarx %ebx,\(%ecx\),%esi
23 [ ]*[a-f0-9]+: c4 e2 79 f7 f3 shlx %eax,%ebx,%esi
24 [ ]*[a-f0-9]+: c4 e2 61 f7 31 shlx %ebx,\(%ecx\),%esi
25 [ ]*[a-f0-9]+: c4 e2 7b f7 f3 shrx %eax,%ebx,%esi
26 [ ]*[a-f0-9]+: c4 e2 63 f7 31 shrx %ebx,\(%ecx\),%esi
42 [ ]*[a-f0-9]+: c4 e2 7a f7 f3 sarx %eax,%ebx,%esi
43 [ ]*[a-f0-9]+: c4 e2 62 f7 31 sarx %ebx,\(%ecx\),%esi
44 [ ]*[a-f0-9]+: c4 e2 62 f7 31 sarx %ebx,\(%ecx\),%esi
45 [ ]*[a-f0-9]+: c4 e2 79 f7 f3 shlx %eax,%ebx,%es
[all...] |
| x86-64-bmi2-intel.d | 32 [ ]*[a-f0-9]+: c4 e2 7a f7 f3 sarx esi,ebx,eax
33 [ ]*[a-f0-9]+: c4 e2 62 f7 31 sarx esi,DWORD PTR \[rcx\],ebx
34 [ ]*[a-f0-9]+: c4 42 32 f7 d7 sarx r10d,r15d,r9d
35 [ ]*[a-f0-9]+: c4 62 32 f7 11 sarx r10d,DWORD PTR \[rcx\],r9d
36 [ ]*[a-f0-9]+: c4 e2 79 f7 f3 shlx esi,ebx,eax
37 [ ]*[a-f0-9]+: c4 e2 61 f7 31 shlx esi,DWORD PTR \[rcx\],ebx
38 [ ]*[a-f0-9]+: c4 42 31 f7 d7 shlx r10d,r15d,r9d
39 [ ]*[a-f0-9]+: c4 62 31 f7 11 shlx r10d,DWORD PTR \[rcx\],r9d
40 [ ]*[a-f0-9]+: c4 e2 7b f7 f3 shrx esi,ebx,eax
41 [ ]*[a-f0-9]+: c4 e2 63 f7 31 shrx esi,DWORD PTR \[rcx\],eb
[all...] |
| x86-64-bmi2.d | 31 [ ]*[a-f0-9]+: c4 e2 7a f7 f3 sarx %eax,%ebx,%esi
32 [ ]*[a-f0-9]+: c4 e2 62 f7 31 sarx %ebx,\(%rcx\),%esi
33 [ ]*[a-f0-9]+: c4 42 32 f7 d7 sarx %r9d,%r15d,%r10d
34 [ ]*[a-f0-9]+: c4 62 32 f7 11 sarx %r9d,\(%rcx\),%r10d
35 [ ]*[a-f0-9]+: c4 e2 79 f7 f3 shlx %eax,%ebx,%esi
36 [ ]*[a-f0-9]+: c4 e2 61 f7 31 shlx %ebx,\(%rcx\),%esi
37 [ ]*[a-f0-9]+: c4 42 31 f7 d7 shlx %r9d,%r15d,%r10d
38 [ ]*[a-f0-9]+: c4 62 31 f7 11 shlx %r9d,\(%rcx\),%r10d
39 [ ]*[a-f0-9]+: c4 e2 7b f7 f3 shrx %eax,%ebx,%esi
40 [ ]*[a-f0-9]+: c4 e2 63 f7 31 shrx %ebx,\(%rcx\),%es
[all...] |
| /external/mesa3d/src/mesa/sparc/ |
| norm.S | 58 * tz (f7) = (ux * m8) + (uy * m9) + (uz * m10)
64 fmuls %f0, M8, %f7 ! FGM Group f3 available
70 fmuls %f2, M10, %f4 ! FGM Group f7 available
71 fadds %f7, %f8, %f7 ! FGA Group f8,f3 available
74 fadds %f7, %f4, %f7 ! FGA Group stall f4,f7 available
76 /* f3=tx, f5=ty, f7=tz */
81 fmuls %f7, %f7, %f10 ! FGM Group f7 availabl
[all...] |
| /device/linaro/bootloader/edk2/EdkCompatibilityPkg/Compatibility/FvOnFv2Thunk/ |
| FvOnFv2Thunk.inf | 27 FILE_GUID = 5007A40E-A5E0-44f7-86AE-662F9A91DA26
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/i860/ |
| dual02-err.s | 7 d.fadd.ss %f3,%f5,%f7
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/sh/ |
| dsp.d | 10 0+002 <[^>]*> f7 94 [ ]*movs.w @r3,x1
15 0+00c <[^>]*> f7 79 [ ]*movs.w a0,@r3\+
18 0+012 <[^>]*> f7 d6 [ ]*movs.l @r3,a1g
23 0+01c <[^>]*> f7 cb [ ]*movs.l m0,@r3\+
|
