| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/mips/ |
| mips64-mips3d.s | 11 bc1any2f $fcc0, text_label
16 bc1any2t $fcc0, text_label
21 bc1any4f $fcc0, text_label
26 bc1any4t $fcc0, text_label
31 cabs.f.d $fcc0, $f8, $f19
33 cabs.f.s $fcc0, $f8, $f19
35 cabs.f.ps $fcc0, $f8, $f19
37 cabs.un.d $fcc0, $f8, $f19
39 cabs.un.s $fcc0, $f8, $f19
41 cabs.un.ps $fcc0, $f8, $f1
[all...] |
| mips64-mips3d-incl.d | 15 0+0004 <[^>]*> 4520fffe bc1any2f \$fcc0,0+0000 <text_label>
19 0+0014 <[^>]*> 4521fffa bc1any2t \$fcc0,0+0000 <text_label>
23 0+0024 <[^>]*> 4540fff6 bc1any4f \$fcc0,0+0000 <text_label>
27 0+0034 <[^>]*> 4541fff2 bc1any4t \$fcc0,0+0000 <text_label>
31 0+0044 <[^>]*> 46334070 cabs\.f\.d \$fcc0,\$f8,\$f19
33 0+004c <[^>]*> 46134070 cabs\.f\.s \$fcc0,\$f8,\$f19
35 0+0054 <[^>]*> 46d34070 cabs\.f\.ps \$fcc0,\$f8,\$f19
37 0+005c <[^>]*> 46334071 cabs\.un\.d \$fcc0,\$f8,\$f19
39 0+0064 <[^>]*> 46134071 cabs\.un\.s \$fcc0,\$f8,\$f19
41 0+006c <[^>]*> 46d34071 cabs\.un\.ps \$fcc0,\$f8,\$f1
[all...] |
| mips64-mips3d.d | 12 0+0004 <[^>]*> 4520fffe bc1any2f \$fcc0,0+0000 <text_label>
16 0+0014 <[^>]*> 4521fffa bc1any2t \$fcc0,0+0000 <text_label>
20 0+0024 <[^>]*> 4540fff6 bc1any4f \$fcc0,0+0000 <text_label>
24 0+0034 <[^>]*> 4541fff2 bc1any4t \$fcc0,0+0000 <text_label>
28 0+0044 <[^>]*> 46334070 cabs\.f\.d \$fcc0,\$f8,\$f19
30 0+004c <[^>]*> 46134070 cabs\.f\.s \$fcc0,\$f8,\$f19
32 0+0054 <[^>]*> 46d34070 cabs\.f\.ps \$fcc0,\$f8,\$f19
34 0+005c <[^>]*> 46334071 cabs\.un\.d \$fcc0,\$f8,\$f19
36 0+0064 <[^>]*> 46134071 cabs\.un\.s \$fcc0,\$f8,\$f19
38 0+006c <[^>]*> 46d34071 cabs\.un\.ps \$fcc0,\$f8,\$f1
[all...] |
| mips4-fp.s | 15 movf.d $f4,$f6,$fcc0
16 movf.s $f4,$f6,$fcc0
20 movt.d $f4,$f6,$fcc0
21 movt.s $f4,$f6,$fcc0
|
| mips4-fp.d | 22 [0-9a-f]+ <[^>]*> movf.d \$f4,\$f6,\$fcc0
23 [0-9a-f]+ <[^>]*> movf.s \$f4,\$f6,\$fcc0
27 [0-9a-f]+ <[^>]*> movt.d \$f4,\$f6,\$fcc0
28 [0-9a-f]+ <[^>]*> movt.s \$f4,\$f6,\$fcc0
|
| set-arch.s | 52 movf.d $f4,$f6,$fcc0
53 movf.s $f4,$f6,$fcc0
58 movt.d $f4,$f6,$fcc0
59 movt.s $f4,$f6,$fcc0
|
| micromips@mips4-fp.d | 27 [0-9a-f]+ <[^>]*> 5486 0220 movf\.d \$f4,\$f6,\$fcc0
28 [0-9a-f]+ <[^>]*> 5486 0020 movf\.s \$f4,\$f6,\$fcc0
32 [0-9a-f]+ <[^>]*> 5486 0260 movt\.d \$f4,\$f6,\$fcc0
33 [0-9a-f]+ <[^>]*> 5486 0060 movt\.s \$f4,\$f6,\$fcc0
|
| /art/runtime/interpreter/mterp/mips/ |
| op_float_to_int.S | 18 c.ole.s fcc0, fa1, fa0
22 bc1t fcc0, 1f # if INT_MIN <= vB, proceed to truncation
23 c.eq.s fcc0, fa0, fa0
25 movt.s fa0, fa1, fcc0 # fa0 = ordered(vB) ? INT_MIN_AS_FLOAT : 0
|
| op_cmpl_float.S | 31 c.eq.s fcc0, ft0, ft1
33 bc1t fcc0, 1f # done if vBB == vCC (ordered)
35 c.olt.s fcc0, ft0, ft1
37 bc1t fcc0, 1f # done if vBB < vCC (ordered)
40 c.olt.s fcc0, ft1, ft0
42 bc1t fcc0, 1f # done if vBB > vCC (ordered)
|
| op_double_to_long.S | 21 c.eq.d fcc0, fa0, fa0
24 bc1f fcc0, .L${opcode}_get_opcode
29 c.ole.d fcc0, fa0, fa1
31 bc1t fcc0, .L${opcode}_get_opcode
34 c.ole.d fcc0, fa1, fa0
37 bc1t fcc0, .L${opcode}_get_opcode
|
| op_float_to_long.S | 20 c.eq.s fcc0, fa0, fa0
23 bc1f fcc0, .L${opcode}_get_opcode
27 c.ole.s fcc0, fa0, fa1
29 bc1t fcc0, .L${opcode}_get_opcode
32 c.ole.s fcc0, fa1, fa0
35 bc1t fcc0, .L${opcode}_get_opcode
|
| op_double_to_int.S | 19 c.ole.d fcc0, fa1, fa0
23 bc1t fcc0, 1f # if INT_MIN <= vB, proceed to truncation
24 c.eq.d fcc0, fa0, fa0
27 movt.d fa0, fa1, fcc0 # fa0 = ordered(vB) ? INT_MIN_AS_DOUBLE : 0
|
| op_cmpl_double.S | 33 c.eq.d fcc0, ft0, ft1
35 bc1t fcc0, 1f # done if vBB == vCC (ordered)
37 c.olt.d fcc0, ft0, ft1
39 bc1t fcc0, 1f # done if vBB < vCC (ordered)
42 c.olt.d fcc0, ft1, ft0
44 bc1t fcc0, 1f # done if vBB > vCC (ordered)
|
| /external/llvm/test/MC/Mips/ |
| micromips-movcond-instructions.s | 14 # CHECK-EL: movt $9, $6, $fcc0 # encoding: [0x26,0x55,0x7b,0x09]
15 # CHECK-EL: movf $9, $6, $fcc0 # encoding: [0x26,0x55,0x7b,0x01]
21 # CHECK-EB: movt $9, $6, $fcc0 # encoding: [0x55,0x26,0x09,0x7b]
22 # CHECK-EB: movf $9, $6, $fcc0 # encoding: [0x55,0x26,0x01,0x7b]
25 movt $9, $6, $fcc0
26 movf $9, $6, $fcc0
|
| micromips-bad-branches.s | 103 # CHECK: bc1f $fcc0, -65535
105 # CHECK: bc1f $fcc0, -65537
107 # CHECK: bc1f $fcc0, 65535
109 # CHECK: bc1f $fcc0, 65536
121 # CHECK: bc1t $fcc0, -65535
123 # CHECK: bc1t $fcc0, -65537
125 # CHECK: bc1t $fcc0, 65535
127 # CHECK: bc1t $fcc0, 65536
211 bc1f $fcc0, -65535
212 bc1f $fcc0, -6553
[all...] |
| mips-bad-branches.s | 191 # CHECK: bc1f $fcc0, -131069
193 # CHECK: bc1f $fcc0, -131070
195 # CHECK: bc1f $fcc0, -131071
197 # CHECK: bc1f $fcc0, -131073
199 # CHECK: bc1f $fcc0, 131069
201 # CHECK: bc1f $fcc0, 131070
203 # CHECK: bc1f $fcc0, 131071
205 # CHECK: bc1f $fcc0, 131072
225 # CHECK: bc1t $fcc0, -131069
227 # CHECK: bc1t $fcc0, -13107
[all...] |
| /external/valgrind/none/tests/mips32/ |
| MoveIns.stdout.exp | 114 movf $t0, $t1, $fcc0 :: out: 0x0, RDval: 0x0, RSval: 0xffffffff, cc: 1
115 movf $t0, $t1, $fcc0 :: out: 0xffffffff, RDval: 0xffffffff, RSval: 0xffffffff, cc: 0
116 movf $t0, $t1, $fcc0 :: out: 0x22b, RDval: 0x22b, RSval: 0xffffffff, cc: 1
117 movf $t0, $t1, $fcc0 :: out: 0x5, RDval: 0x0, RSval: 0x5, cc: 0
118 movf $t0, $t1, $fcc0 :: out: 0x0, RDval: 0x0, RSval: 0xffffffff, cc: 1
119 movf $t0, $t1, $fcc0 :: out: 0x19, RDval: 0xffffffff, RSval: 0x19, cc: 0
120 movf $t0, $t1, $fcc0 :: out: 0xffffffff, RDval: 0xffffffff, RSval: 0x0, cc: 1
121 movf $t0, $t1, $fcc0 :: out: 0x42, RDval: 0xffffffff, RSval: 0x42, cc: 0
131 movf.s $f4, $f6, $fcc0 :: out: 456.248962, cc: 1
132 movf.s $f4, $f6, $fcc0 :: out: 456.248962, cc:
[all...] |
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/frv/ |
| allinsn.d | 850 460: b8 1c fe e8 fbne fcc0,0x0,0 <add>
853 464: c0 1c fe e7 fbeq fcc0,0x0,0 <add>
856 468: b0 1c fe e6 fblg fcc0,0x0,0 <add>
859 46c: c8 1c fe e5 fbue fcc0,0x0,0 <add>
862 470: a8 1c fe e4 fbul fcc0,0x0,0 <add>
865 474: d0 1c fe e3 fbge fcc0,0x0,0 <add>
868 478: a0 1c fe e2 fblt fcc0,0x0,0 <add>
871 47c: d8 1c fe e1 fbuge fcc0,0x0,0 <add>
874 480: 98 1c fe e0 fbug fcc0,0x0,0 <add>
877 484: e0 1c fe df fble fcc0,0x0,0 <add
[all...] |
| allinsn.s | 1128 fbne fcc0,0,footext
1132 fbeq fcc0,0,footext
1136 fblg fcc0,0,footext
1140 fbue fcc0,0,footext
1144 fbul fcc0,0,footext
1148 fbge fcc0,0,footext
1152 fblt fcc0,0,footext
1156 fbuge fcc0,0,footext
1160 fbug fcc0,0,footext
1164 fble fcc0,0,footex
[all...] |
| /external/llvm/test/MC/Sparc/ |
| sparc64-ctrl-instructions.s | 119 ! CHECK: movu %fcc0, %g1, %g2 ! encoding: [0x85,0x61,0xc0,0x01]
120 ! CHECK: movg %fcc0, %g1, %g2 ! encoding: [0x85,0x61,0x80,0x01]
121 ! CHECK: movug %fcc0, %g1, %g2 ! encoding: [0x85,0x61,0x40,0x01]
122 ! CHECK: movl %fcc0, %g1, %g2 ! encoding: [0x85,0x61,0x00,0x01]
123 ! CHECK: movul %fcc0, %g1, %g2 ! encoding: [0x85,0x60,0xc0,0x01]
124 ! CHECK: movlg %fcc0, %g1, %g2 ! encoding: [0x85,0x60,0x80,0x01]
125 ! CHECK: movne %fcc0, %g1, %g2 ! encoding: [0x85,0x60,0x40,0x01]
126 ! CHECK: move %fcc0, %g1, %g2 ! encoding: [0x85,0x62,0x40,0x01]
127 ! CHECK: movue %fcc0, %g1, %g2 ! encoding: [0x85,0x62,0x80,0x01]
128 ! CHECK: movge %fcc0, %g1, %g2 ! encoding: [0x85,0x62,0xc0,0x01
[all...] |
| /external/llvm/test/MC/Mips/mips3/ |
| invalid-mips4.s | 12 movf $gp,$8,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
14 movf.d $f6,$f11,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
16 movf.s $f23,$f5,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
21 movt $zero,$s4,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
23 movt.d $f0,$f2,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
24 movt.s $f30,$f2,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| invalid-mips5.s | 13 movf $gp,$8,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
15 movf.d $f6,$f11,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
17 movf.s $f23,$f5,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
22 movt $zero,$s4,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
24 movt.d $f0,$f2,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
25 movt.s $f30,$f2,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/llvm/test/MC/Mips/mips32r6/ |
| invalid-mips32-wrong-error.s | 10 bc2f $fcc0,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
12 bc2t $fcc0,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
|
| /external/llvm/test/MC/Mips/mips64r6/ |
| invalid-mips32-wrong-error.s | 9 bc2f $fcc0,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
13 bc2t $fcc0,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
|
| /external/llvm/test/MC/Mips/mips2/ |
| invalid-mips32.s | 22 movf $gp,$8,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
24 movf.d $f6,$f11,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
26 movf.s $f23,$f5,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
31 movt $zero,$s4,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
33 movt.d $f0,$f2,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
34 movt.s $f30,$f2,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
