| /external/llvm/lib/Target/Hexagon/ |
| HexagonRDF.cpp | 53 unsigned Lo = TRI.getSubReg(RR.Reg, Hexagon::subreg_loreg);
54 unsigned Hi = TRI.getSubReg(RR.Reg, Hexagon::subreg_hireg);
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| HexagonRDFOpt.cpp | 108 assert(DstOp.getSubReg() == 0 && "Unexpected subregister");
110 { HiOp.getReg(), HiOp.getSubReg() });
112 { LoOp.getReg(), LoOp.getSubReg() });
124 mapRegs({ DstOp.getReg(), DstOp.getSubReg() },
125 { SrcOp.getReg(), SrcOp.getSubReg() });
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| HexagonAsmPrinter.cpp | 413 unsigned High = RI->getSubReg(MO1.getReg(), Hexagon::subreg_hireg);
414 unsigned Low = RI->getSubReg(MO1.getReg(), Hexagon::subreg_loreg);
501 unsigned High = RI->getSubReg(MO.getReg(), Hexagon::subreg_hireg);
502 unsigned Low = RI->getSubReg(MO.getReg(), Hexagon::subreg_loreg);
513 unsigned High = RI->getSubReg(MO.getReg(), Hexagon::subreg_hireg);
514 unsigned Low = RI->getSubReg(MO.getReg(), Hexagon::subreg_loreg);
526 unsigned High = RI->getSubReg(MO.getReg(), Hexagon::subreg_hireg);
527 unsigned Low = RI->getSubReg(MO.getReg(), Hexagon::subreg_loreg);
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| HexagonSplitConst32AndConst64.cpp | 140 unsigned DestLo = TRI->getSubReg(DestReg, Hexagon::subreg_loreg);
141 unsigned DestHi = TRI->getSubReg(DestReg, Hexagon::subreg_hireg);
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| HexagonPeephole.cpp | 211 if (Src.getSubReg() != Hexagon::subreg_loreg)
306 Dst.setSubReg(Src.getSubReg());
321 Dst.setSubReg(Src.getSubReg());
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| HexagonSplitDouble.cpp | 237 if (&MO == &Op || !MO.isReg() || MO.getSubReg())
306 if (!Op.getSubReg())
310 if (MI->getOperand(1).getSubReg() != 0)
398 if (Op.getSubReg())
561 unsigned SR = Op.getSubReg();
608 .addReg(AdrOp.getReg(), RSA & ~RegState::Kill, AdrOp.getSubReg())
611 .addReg(AdrOp.getReg(), RSA & ~RegState::Kill, AdrOp.getSubReg())
617 .addReg(AdrOp.getReg(), RSA & ~RegState::Kill, AdrOp.getSubReg())
621 .addReg(AdrOp.getReg(), RSA & ~RegState::Kill, AdrOp.getSubReg())
633 assert(!UpdOp.getSubReg() && "Def operand with subreg")
[all...] |
| HexagonInstrInfo.cpp | 115 return isIntRegForSubInst(HRI.getSubReg(Reg, Hexagon::subreg_loreg)) &&
116 isIntRegForSubInst(HRI.getSubReg(Reg, Hexagon::subreg_hireg));
826 .addReg(HRI.getSubReg(SrcReg, Hexagon::subreg_hireg), KillFlag)
827 .addReg(HRI.getSubReg(SrcReg, Hexagon::subreg_loreg), KillFlag);
847 unsigned DstHi = HRI.getSubReg(DestReg, Hexagon::subreg_hireg);
849 .addReg(HRI.getSubReg(SrcReg, Hexagon::subreg_hireg), KillFlag);
850 unsigned DstLo = HRI.getSubReg(DestReg, Hexagon::subreg_loreg);
852 .addReg(HRI.getSubReg(SrcReg, Hexagon::subreg_loreg), KillFlag);
[all...] |
| RDFCopy.cpp | 35 RegisterRef DstR = { Dst.getReg(), Dst.getSubReg() };
36 RegisterRef SrcR = { Src.getReg(), Src.getSubReg() };
59 RegisterRef DefR = { Dst.getReg(), Dst.getSubReg() };
|
| /external/llvm/lib/Target/AMDGPU/ |
| SIFrameLowering.cpp | 106 unsigned FlatScrInitHi = TRI->getSubReg(FlatScratchInitReg, AMDGPU::sub1);
110 unsigned FlatScrInitLo = TRI->getSubReg(FlatScratchInitReg, AMDGPU::sub0);
227 unsigned Rsrc01 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub0_sub1);
228 unsigned Rsrc23 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub2_sub3);
230 unsigned Lo = TRI->getSubReg(PreloadedPrivateBufferReg, AMDGPU::sub0_sub1);
231 unsigned Hi = TRI->getSubReg(PreloadedPrivateBufferReg, AMDGPU::sub2_sub3);
240 unsigned Rsrc0 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub0);
241 unsigned Rsrc1 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub1);
242 unsigned Rsrc2 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub2);
243 unsigned Rsrc3 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub3)
[all...] |
| R600ExpandSpecialInstrs.cpp | 187 TRI.getSubReg(DstReg, TRI.getSubRegFromChannel(Chan)), PReg);
287 Src0 = TRI.getSubReg(Src0, SubRegIndex);
288 Src1 = TRI.getSubReg(Src1, SubRegIndex);
293 Src1 = TRI.getSubReg(Src0, SubRegIndex1);
294 Src0 = TRI.getSubReg(Src0, SubRegIndex0);
302 DstReg = TRI.getSubReg(DstReg, SubRegIndex);
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| SIFoldOperands.cpp | 113 Old.substVirtReg(New->getReg(), New->getSubReg(), TRI);
200 if (UseOp.isReg() && ((UseOp.getSubReg() && OpToFold.isReg()) ||
222 if (FoldRC->getSize() == 8 && UseOp.getSubReg()) {
226 if (UseOp.getSubReg() == AMDGPU::sub0) {
229 assert(UseOp.getSubReg() == AMDGPU::sub1);
264 if (RSUse->getSubReg() != RegSeqDstSubReg)
|
| /external/swiftshader/third_party/LLVM/lib/CodeGen/ |
| CalcSpillWeights.cpp | 64 sub = mi->getOperand(0).getSubReg();
66 hsub = mi->getOperand(1).getSubReg();
68 sub = mi->getOperand(1).getSubReg();
70 hsub = mi->getOperand(0).getSubReg();
|
| ProcessImplicitDefs.cpp | 53 return MI->isCopy() && (MI->getOperand(0).getSubReg() == 0 ||
56 return MI->isSubregToReg() && (MI->getOperand(0).getSubReg() == 0 ||
69 if (!MO0.getSubReg() || ImpDefRegs.count(MO0.getReg()))
108 if (MI->getOperand(0).getSubReg())
121 if (MI->isCopy() && MI->getOperand(0).getSubReg()) {
143 if (!MO.isReg() || (MO.isDef() && !MO.getSubReg()) || MO.isUndef())
|
| OptimizePHIs.cpp | 107 !SrcMI->getOperand(0).getSubReg() &&
108 !SrcMI->getOperand(1).getSubReg() &&
|
| /external/llvm/lib/MC/ |
| MCRegisterInfo.cpp | 21 if (RC->contains(*Supers) && Reg == getSubReg(*Supers, SubIdx))
26 unsigned MCRegisterInfo::getSubReg(unsigned Reg, unsigned Idx) const {
|
| /external/llvm/lib/CodeGen/ |
| PeepholeOptimizer.cpp | 465 if (UseSrcSubIdx && UseMO.getSubReg() != SubIdx)
792 SrcSubReg = MOSrc.getSubReg();
796 TrackSubReg = MODef.getSubReg();
[all...] |
| CalcSpillWeights.cpp | 51 sub = mi->getOperand(0).getSubReg();
53 hsub = mi->getOperand(1).getSubReg();
55 sub = mi->getOperand(1).getSubReg();
57 hsub = mi->getOperand(0).getSubReg();
|
| TargetRegisterInfo.cpp | 218 if (RCI.getSubReg() == Idx)
257 unsigned FinalA = composeSubRegIndices(IA.getSubReg(), SubA);
266 unsigned FinalB = composeSubRegIndices(IB.getSubReg(), SubB);
276 *BestPreA = IA.getSubReg();
277 *BestPreB = IB.getSubReg();
|
| DetectDeadLanes.cpp | 165 unsigned SrcSubIdx = MO.getSubReg();
204 unsigned MOSubReg = MO.getSubReg();
300 TRI->reverseComposeSubRegIndexLaneMask(Use.getSubReg(), DefinedLanes);
349 assert(Def.getSubReg() == 0 &&
401 unsigned MOSubReg = MO.getSubReg();
415 assert(Def.getSubReg() == 0 &&
430 unsigned SubReg = MO.getSubReg();
463 unsigned SubReg = MO.getSubReg();
|
| OptimizePHIs.cpp | 111 !SrcMI->getOperand(0).getSubReg() &&
112 !SrcMI->getOperand(1).getSubReg() &&
|
| /external/llvm/lib/Target/Sparc/ |
| SparcRegisterInfo.cpp | 183 unsigned SrcEvenReg = getSubReg(SrcReg, SP::sub_even64);
184 unsigned SrcOddReg = getSubReg(SrcReg, SP::sub_odd64);
195 unsigned DestEvenReg = getSubReg(DestReg, SP::sub_even64);
196 unsigned DestOddReg = getSubReg(DestReg, SP::sub_odd64);
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64AdvSIMDScalarPass.cpp | 152 if (isFPR64(MI->getOperand(0).getReg(), MI->getOperand(0).getSubReg(),
154 isGPR64(MI->getOperand(1).getReg(), MI->getOperand(1).getSubReg(), MRI))
156 if (isGPR64(MI->getOperand(0).getReg(), MI->getOperand(0).getSubReg(),
158 isFPR64(MI->getOperand(1).getReg(), MI->getOperand(1).getSubReg(),
160 SubReg = MI->getOperand(1).getSubReg();
|
| /external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
| MachineInstr.h | 288 return isCopy() && !getOperand(0).getSubReg() && !getOperand(1).getSubReg();
300 getOperand(0).getSubReg() == getOperand(1).getSubReg();
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCVSXFMAMutate.cpp | 220 unsigned AddSubReg = AddendMI->getOperand(1).getSubReg();
221 unsigned KilledProdSubReg = MI->getOperand(KilledProdOp).getSubReg();
222 unsigned OtherProdSubReg = MI->getOperand(OtherProdOp).getSubReg();
|
| PPCQPXLoadSplat.cpp | 110 unsigned SplatSubReg = TRI->getSubReg(SplatReg, SubRegIndex);
|
