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  /toolchain/binutils/binutils-2.25/ld/testsuite/ld-crx/
reloc-imm16.d 1 #source: reloc-imm16.s
  /toolchain/binutils/binutils-2.25/gas/testsuite/gas/cr16/
sub_test.s 5 # SUBB imm4/imm16, reg
23 # SUBCB imm4/imm16, reg
41 # SUBCW imm4/imm16, reg
59 # SUBW imm4/imm16, reg
77 # SUBD imm4/imm16/imm32, regp
and_test.s 5 # ANDB imm4/imm16, reg
23 # ANDW imm4/imm16, reg
41 # ANDD imm4/imm16/imm32, regp
cmp_test.s 5 # CMPB imm4/imm16, reg
24 # CMPW imm4/imm16, reg
44 # CMPD imm4/imm16/imm32, regp
add_test.s 5 # ADDB imm4/imm16, reg
24 # ADDCB imm4/imm16, reg
43 # ADDCW imm4/imm16, reg
62 # ADDW imm4/imm16, reg
80 # ADDD imm4/imm16/imm20/imm32, regp
mul_test.s 5 # MULB imm4/imm16, reg
23 # MULW imm4/imm16, reg
or_test.s 5 # ORB imm4/imm16, reg
23 # ORW imm4/imm16, reg
xor_test.s 5 # XORB imm4/imm16, reg
23 # XORW imm4/imm16, reg
mov_test.s 5 # MOVB imm4/imm16, reg
24 # MOVW imm4/imm16, reg
44 # MOVD imm4/imm16/imm20/imm32, regp
  /toolchain/binutils/binutils-2.25/opcodes/
cr16-opc.c 32 /* opc8 imm16 r */ \
37 /* For Logical operations, allow unsigned imm16 also. */
39 /* opc8 imm16 r */ \
44 ARITH1_BYTE_INST ("andb", 0x20, imm16),
46 ARITH1_BYTE_INST ("andw", 0x22, imm16),
49 ARITH1_BYTE_INST ("orb", 0x24, imm16),
51 ARITH1_BYTE_INST ("orw", 0x26, imm16),
54 ARITH1_BYTE_INST ("xorb", 0x28, imm16),
56 ARITH1_BYTE_INST ("xorw", 0x2A, imm16),
58 ARITH_BYTE_INST ("addub", 0x2C, imm16),
    [all...]
dlx-dis.c 40 unsigned long imm26, imm16, func, current_insn_addr; variable
215 (*info->fprintf_func) (info->stream, "0x%04x", (int)imm16);
222 (*info->fprintf_func) (info->stream, "0x%04x[r%d]", (int)imm16, (int)rs1);
256 (*info->fprintf_func) (info->stream, "0x%04x[r%d],", (int)imm16, (int)rs1);
314 (*info->fprintf_func) (info->stream, "0x%04x", (int)imm16);
344 if (imm16 & 0x00008000)
345 imm16 |= 0xFFFF0000;
347 imm16 += (current_insn_addr + 4);
351 (*info->fprintf_func) (info->stream, "0x%08x", (int) imm16);
468 imm16= dlx_get_imm16 (insn_word)
    [all...]
  /art/compiler/utils/mips/
assembler_mips.h 218 void Addiu(Register rt, Register rs, uint16_t imm16);
239 void Andi(Register rt, Register rs, uint16_t imm16);
241 void Ori(Register rt, Register rs, uint16_t imm16);
243 void Xori(Register rt, Register rs, uint16_t imm16);
273 void Lb(Register rt, Register rs, uint16_t imm16);
274 void Lh(Register rt, Register rs, uint16_t imm16);
275 void Lw(Register rt, Register rs, uint16_t imm16);
276 void Lwl(Register rt, Register rs, uint16_t imm16);
277 void Lwr(Register rt, Register rs, uint16_t imm16);
278 void Lbu(Register rt, Register rs, uint16_t imm16);
    [all...]
assembler_mips.cc 534 void MipsAssembler::Addiu(Register rt, Register rs, uint16_t imm16) {
535 DsFsmInstrRrr(EmitI(0x9, rs, rt, imm16), rt, rs, rs);
630 void MipsAssembler::Andi(Register rt, Register rs, uint16_t imm16) {
631 DsFsmInstrRrr(EmitI(0xc, rs, rt, imm16), rt, rs, rs);
638 void MipsAssembler::Ori(Register rt, Register rs, uint16_t imm16) {
639 DsFsmInstrRrr(EmitI(0xd, rs, rt, imm16), rt, rs, rs);
646 void MipsAssembler::Xori(Register rt, Register rs, uint16_t imm16) {
647 DsFsmInstrRrr(EmitI(0xe, rs, rt, imm16), rt, rs, rs);
786 void MipsAssembler::Lb(Register rt, Register rs, uint16_t imm16) {
787 DsFsmInstrRrr(EmitI(0x20, rs, rt, imm16), rt, rs, rs)
1174 Bc1f(static_cast<int>(rs), imm16); local
1178 Bc1t(static_cast<int>(rs), imm16); local
    [all...]
  /art/compiler/utils/mips64/
assembler_mips64.h 446 void Addiu(GpuRegister rt, GpuRegister rs, uint16_t imm16);
448 void Daddiu(GpuRegister rt, GpuRegister rs, uint16_t imm16); // MIPS64
466 void Andi(GpuRegister rt, GpuRegister rs, uint16_t imm16);
468 void Ori(GpuRegister rt, GpuRegister rs, uint16_t imm16);
470 void Xori(GpuRegister rt, GpuRegister rs, uint16_t imm16);
510 void Lb(GpuRegister rt, GpuRegister rs, uint16_t imm16);
511 void Lh(GpuRegister rt, GpuRegister rs, uint16_t imm16);
512 void Lw(GpuRegister rt, GpuRegister rs, uint16_t imm16);
513 void Ld(GpuRegister rt, GpuRegister rs, uint16_t imm16); // MIPS64
514 void Lbu(GpuRegister rt, GpuRegister rs, uint16_t imm16);
    [all...]
assembler_mips64.cc 307 void Mips64Assembler::Addiu(GpuRegister rt, GpuRegister rs, uint16_t imm16) {
308 EmitI(0x9, rs, rt, imm16);
315 void Mips64Assembler::Daddiu(GpuRegister rt, GpuRegister rs, uint16_t imm16) {
316 EmitI(0x19, rs, rt, imm16);
379 void Mips64Assembler::Andi(GpuRegister rt, GpuRegister rs, uint16_t imm16) {
380 EmitI(0xc, rs, rt, imm16);
387 void Mips64Assembler::Ori(GpuRegister rt, GpuRegister rs, uint16_t imm16) {
388 EmitI(0xd, rs, rt, imm16);
395 void Mips64Assembler::Xori(GpuRegister rt, GpuRegister rs, uint16_t imm16) {
396 EmitI(0xe, rs, rt, imm16);
    [all...]
  /external/valgrind/none/tests/x86/
insn_basic.def 35 adcw eflags[0x1,0x0] : imm16[1234] ax.uw[5678] => 1.uw[6912]
36 adcw eflags[0x1,0x1] : imm16[1234] ax.uw[5678] => 1.uw[6913]
37 adcw eflags[0x1,0x0] : imm16[1234] bx.uw[5678] => 1.uw[6912]
38 adcw eflags[0x1,0x1] : imm16[1234] bx.uw[5678] => 1.uw[6913]
39 adcw eflags[0x1,0x0] : imm16[1234] m16.uw[5678] => 1.uw[6912]
40 adcw eflags[0x1,0x1] : imm16[1234] m16.uw[5678] => 1.uw[6913]
68 addw imm16[1234] ax.uw[5678] => 1.uw[6912]
69 addw imm16[1234] bx.uw[5678] => 1.uw[6912]
70 addw imm16[1234] m16.uw[5678] => 1.uw[6912]
88 andw imm16[0x4231] ax.uw[0x1234] => 1.uw[0x0230
    [all...]
  /external/v8/src/ppc/
assembler-ppc.cc 479 int imm16 = target_pos - pos; local
480 CHECK(is_int16(imm16) && (imm16 & (kAAMask | kLKMask)) == 0);
481 if (imm16 == kInstrSize && !(instr & kLKMask)) {
486 instr |= (imm16 & kImm16Mask);
746 int imm16 = branch_offset; local
747 CHECK(is_int16(imm16) && (imm16 & (kAAMask | kLKMask)) == 0);
748 emit(BCX | bo | condition_bit * B16 | (imm16 & kImm16Mask) | lk);
1023 intptr_t imm16 = src2.imm_ local
1075 intptr_t imm16 = src2.imm_; local
2006 int imm16 = offset & kImm16Mask; local
2017 int imm16 = offset & kImm16Mask; local
2046 int imm16 = offset & kImm16Mask; local
2057 int imm16 = offset & kImm16Mask; local
2086 int imm16 = offset & kImm16Mask; local
2097 int imm16 = offset & kImm16Mask; local
2126 int imm16 = offset & kImm16Mask; local
2137 int imm16 = offset & kImm16Mask; local
    [all...]
  /external/v8/src/x87/
assembler-x87.cc 422 void Assembler::mov_w(const Operand& dst, int16_t imm16) {
427 EMIT(static_cast<int8_t>(imm16 & 0xff));
428 EMIT(static_cast<int8_t>(imm16 >> 8));
708 void Assembler::cmpw(const Operand& op, Immediate imm16) {
709 DCHECK(imm16.is_int16());
714 emit_w(imm16);
1190 void Assembler::test_w(Register reg, Immediate imm16) {
1191 DCHECK(imm16.is_int16() || imm16.is_uint16());
1195 emit_w(imm16);
    [all...]
  /device/linaro/bootloader/edk2/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/
SmiEntry.S 47 .byte 0xbb # mov bx, imm16
60 .byte 0xb8 # mov ax, imm16
SmiEntry.asm 54 DB 0bbh ; mov bx, imm16
67 DB 0b8h ; mov ax, imm16
  /device/linaro/bootloader/edk2/UefiCpuPkg/PiSmmCpuDxeSmm/X64/
SmiEntry.asm 68 DB 0bbh ; mov bx, imm16
83 DB 0b8h ; mov ax, imm16
  /toolchain/binutils/binutils-2.25/include/opcode/
cr16.h 122 imm3, imm4, imm5, imm6, imm16, imm20, imm32, enumerator in enum:__anon116248
  /external/v8/src/ia32/
assembler-ia32.cc 837 void Assembler::cmpw(const Operand& op, Immediate imm16) {
838 DCHECK(imm16.is_int16() || imm16.is_uint16());
843 emit_w(imm16);
1319 void Assembler::test_w(Register reg, Immediate imm16) {
1320 DCHECK(imm16.is_int16() || imm16.is_uint16());
1324 emit_w(imm16);
1329 emit_w(imm16);
1340 void Assembler::test_w(const Operand& op, Immediate imm16) {
    [all...]
  /external/valgrind/VEX/priv/
host_mips_defs.c 580 MIPSRH *MIPSRH_Imm(Bool syned, UShort imm16)
585 op->Mrh.Imm.imm16 = imm16;
589 vassert(imm16 != 0x8000);
608 vex_printf("%d", (Int) (Short) op->Mrh.Imm.imm16);
610 vex_printf("%u", (UInt) (UShort) op->Mrh.Imm.imm16);
    [all...]
  /toolchain/binutils/binutils-2.25/gas/testsuite/gas/i386/
hlebad.s 15 # Tests for op imm16 ax
41 # Tests for op imm16 regs/m16
234 # Tests for op imm16 ax
260 # Tests for op imm16 regs/m16

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