| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/mips/ |
| vr4130.d | 13 .* mfhi .*
29 .* mfhi .*
36 .* mfhi .*
43 .* mfhi .*
50 .* mfhi .*
57 .* mfhi .*
64 .* mfhi .*
71 .* mfhi .*
78 .* mfhi .*
85 .* mfhi .
[all...] |
| vr4130.s | 7 mfhi $2
22 mfhi $2
35 mfhi $2
38 mfhi $2
42 mfhi $2
47 mfhi $2
53 mfhi $2
60 mfhi $2
65 mfhi $2
71 mfhi $
[all...] |
| mul-ilocks.d | 37 0+0068 <[^>]*> mfhi at
45 0+0088 <[^>]*> mfhi at
51 0+00a0 <[^>]*> mfhi at
57 0+00b8 <[^>]*> mfhi at
70 0+00ec <[^>]*> mfhi at
76 0+0104 <[^>]*> mfhi at
|
| mul.d | 43 0+008c <[^>]*> mfhi at
52 0+00b4 <[^>]*> mfhi at
59 0+00d4 <[^>]*> mfhi at
65 0+00ec <[^>]*> mfhi at
80 0+012c <[^>]*> mfhi at
87 0+014c <[^>]*> mfhi at
|
| div-ilocks.d | 86 0+0130 <[^>]*> mfhi a0
89 0+013c <[^>]*> mfhi a0
106 0+0180 <[^>]*> mfhi a0
109 0+018c <[^>]*> mfhi a0
|
| div.d | 96 0+015c <[^>]*> mfhi a0
100 0+016c <[^>]*> mfhi a0
120 0+01bc <[^>]*> mfhi a0
124 0+01cc <[^>]*> mfhi a0
|
| relax-swap1.s | 123 mfhi $2
125 mfhi $2
|
| mips16-macro.d | 30 [ 0-9a-f]+: ee10 mfhi \$6
34 [ 0-9a-f]+: ee10 mfhi \$6
38 [ 0-9a-f]+: ea10 mfhi \$2
42 [ 0-9a-f]+: eb10 mfhi \$3
|
| mips16.s | 182 mfhi $3
|
| mips32-dsp.s | 124 mfhi $0,$ac0
|
| relax-swap1-mips1.d | 276 0+0368 <[^>]*> mfhi v0
279 0+0374 <[^>]*> mfhi v0
|
| relax-swap1-mips2.d | 244 0+02e8 <[^>]*> mfhi v0
247 0+02f4 <[^>]*> mfhi v0
|
| /art/runtime/interpreter/mterp/mips/ |
| op_mul_long_2addr.S | 20 mfhi t1
|
| op_mul_long.S | 28 mfhi t1
|
| /external/llvm/test/MC/Mips/mips32r6/ |
| invalid-mips1.s | 15 mfhi $s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
16 mfhi $sp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| invalid-mips2.s | 21 mfhi $s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
22 mfhi $sp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/llvm/test/MC/Mips/mips64r6/ |
| invalid-mips1.s | 18 mfhi $s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
19 mfhi $sp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| invalid-mips2.s | 24 mfhi $s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
25 mfhi $sp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| invalid-mips3.s | 14 mfhi $s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
15 mfhi $sp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| invalid-mips64.s | 23 mfhi $s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
24 mfhi $sp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/llvm/test/MC/Mips/ |
| micromips-16-bit-instructions.s | 43 # CHECK-EL: mfhi $9 # encoding: [0x09,0x46]
98 # CHECK-EB: mfhi $9 # encoding: [0x46,0x09]
151 mfhi $9
|
| /external/llvm/test/MC/Mips/dsp/ |
| valid.s | 57 mfhi $14, $ac1 # CHECK: mfhi $14, $ac1 # encoding: [0x00,0x20,0x70,0x10]
59 mfhi $14 # CHECK: mfhi $14 # encoding: [0x00,0x00,0x70,0x10]
|
| /external/llvm/test/MC/Mips/dspr2/ |
| valid.s | 79 mfhi $14, $ac1 # CHECK: mfhi $14, $ac1 # encoding: [0x00,0x20,0x70,0x10]
81 mfhi $14 # CHECK: mfhi $14 # encoding: [0x00,0x00,0x70,0x10]
|
| /external/llvm/test/MC/Mips/mips1/ |
| valid.s | 63 mfhi $s3
64 mfhi $sp
|
| /external/llvm/test/MC/Mips/mips2/ |
| valid.s | 83 mfhi $s3
84 mfhi $sp
|
