| /device/linaro/bootloader/arm-trusted-firmware/plat/hikey/ |
| pll.c | 48 mmio_write_32((0xf7032000 + 0x000), data);
57 mmio_write_32((0xf7800000 + 0x000), data);
64 mmio_write_32(PERI_SC_PERIPH_CTRL14, 0x2101);
66 mmio_write_32(0xf7032000 + 0x02c, 0x5110103e);
69 mmio_write_32(0xf7032000 + 0x050, data);
70 mmio_write_32(PERI_SC_PERIPH_CTRL14, 0x2101);
81 mmio_write_32((0xf7032000 + 0x374), 0x4a);
82 mmio_write_32((0xf7032000 + 0x368), 0xda);
83 mmio_write_32((0xf7032000 + 0x36c), 0x01);
84 mmio_write_32((0xf7032000 + 0x370), 0x01)
[all...] |
| usb.c | 156 mmio_write_32(DIEPCTL0, 0x8800);
159 mmio_write_32(DOEPCTL0, 0x8000);
162 mmio_write_32(GOTGINT, ~0);
165 mmio_write_32(GINTSTS, ~0);
166 mmio_write_32(DIEPINT0, ~0);
167 mmio_write_32(DOEPINT0, ~0);
168 mmio_write_32(DIEPINT1, ~0);
169 mmio_write_32(DOEPINT1, ~0);
172 mmio_write_32(DIEPMSK, 0x0D);
174 mmio_write_32(DOEPMSK, 0x0D)
[all...] |
| bl1_plat_setup.c | 138 mmio_write_32(0xf8001830, 0);
151 mmio_write_32(0xf701000c, 0);
152 mmio_write_32(0xf7010010, 0);
153 mmio_write_32(0xf7010014, 0);
154 mmio_write_32(0xf7010018, 0);
155 mmio_write_32(0xf701001c, 0);
156 mmio_write_32(0xf7010020, 0);
159 mmio_write_32(0xf701080c, 0x64);
160 mmio_write_32(0xf7010810, 0x54);
161 mmio_write_32(0xf7010814, 0x54)
[all...] |
| bl31_plat_setup.c | 143 mmio_write_32(AO_SC_PERIPH_CLKEN4, data);
150 mmio_write_32(EDMAC_SEC_CTRL, 0x3);
154 mmio_write_32(EDMAC_AXI_CONF(i), (1 << 6) | (1 << 18));
|
| plat_pm.c | 217 mmio_write_32(0xF8001810, 0x2);
229 mmio_write_32(TIMER00_CONTROL, 0);
230 mmio_write_32(TIMER00_LOAD, 0xffffffff);
232 mmio_write_32(TIMER00_CONTROL, 0x82);
258 mmio_write_32(AO_SC_SYS_STAT0, 0x48698284);
269 mmio_write_32(AO_SC_SYS_STAT0, 0x48698284);
|
| bl2_plat_setup.c | 158 mmio_write_32(MEMORY_AXI_CHIP_ADDR, reg);
162 mmio_write_32(MEMORY_AXI_BOARD_TYPE_ADDR, 0x0);
166 mmio_write_32(MEMORY_AXI_BOARD_ID_ADDR, 0x2b);
169 mmio_write_32(ACPU_ARM64_FLAGA, 0x1234);
170 mmio_write_32(ACPU_ARM64_FLAGB, 0x5678);
|
| /device/linaro/bootloader/arm-trusted-firmware/plat/hikey/drivers/ |
| hisi_pwrc.c | 70 mmio_write_32(ACPU_CTRL_BASE + 0x0E4, reg);
74 mmio_write_32(ACPU_CTRL_BASE + 0x0E4, reg);
84 mmio_write_32(ACPU_SC_CPUx_RVBARADDR(0), PWRCTRL_ACPU_ASM_CODE_BASE >> 2);
85 mmio_write_32(ACPU_SC_CPUx_RVBARADDR(1), PWRCTRL_ACPU_ASM_CODE_BASE >> 2);
86 mmio_write_32(ACPU_SC_CPUx_RVBARADDR(2), PWRCTRL_ACPU_ASM_CODE_BASE >> 2);
87 mmio_write_32(ACPU_SC_CPUx_RVBARADDR(3), PWRCTRL_ACPU_ASM_CODE_BASE >> 2);
88 mmio_write_32(ACPU_SC_CPUx_RVBARADDR(4), PWRCTRL_ACPU_ASM_CODE_BASE >> 2);
89 mmio_write_32(ACPU_SC_CPUx_RVBARADDR(5), PWRCTRL_ACPU_ASM_CODE_BASE >> 2);
90 mmio_write_32(ACPU_SC_CPUx_RVBARADDR(6), PWRCTRL_ACPU_ASM_CODE_BASE >> 2);
91 mmio_write_32(ACPU_SC_CPUx_RVBARADDR(7), PWRCTRL_ACPU_ASM_CODE_BASE >> 2)
[all...] |
| sp804_timer.c | 50 mmio_write_32(AO_SC_TIMER_EN0, data);
56 mmio_write_32(AO_SC_PERIPH_CLKEN4, PCLK_TIMER1 | PCLK_TIMER0);
61 mmio_write_32(AO_SC_PERIPH_RSTEN4, PCLK_TIMER1 | PCLK_TIMER0);
66 mmio_write_32(AO_SC_PERIPH_RSTDIS4, PCLK_TIMER1 | PCLK_TIMER0);
72 mmio_write_32(TIMER00_CONTROL, 0);
73 mmio_write_32(TIMER00_LOAD, 0xffffffff);
75 mmio_write_32(TIMER00_CONTROL, 0x82);
|
| dw_mmc.c | 85 mmio_write_32(MMC0_RINTSTS, ~0);
96 mmio_write_32(MMC0_CMD, data);
130 mmio_write_32(MMC0_CLKENA, 0);
137 mmio_write_32(MMC0_CLKENA, 1);
138 mmio_write_32(MMC0_CLKSRC, 0);
139 mmio_write_32(MMC0_CLKDIV, divider);
147 mmio_write_32(MMC0_CTYPE, MMC_8BIT_MODE);
148 mmio_write_32(MMC0_TMOUT, ~0); /* maxium timeout value */
149 mmio_write_32(MMC0_DEBNCE, 0x00ffffff);
150 mmio_write_32(MMC0_BLKSIZ, MMC_BLOCK_SIZE)
[all...] |
| hisi_dvfs.c | 113 mmio_write_32(addr, reg);
281 mmio_write_32(ACPU_SC_VD_DLY_TABLE0_CTRL, 0x1FFF);
282 mmio_write_32(ACPU_SC_VD_DLY_TABLE1_CTRL, 0x1FFFFFF);
283 mmio_write_32(ACPU_SC_VD_DLY_TABLE2_CTRL, 0x7FFFFFFF);
284 mmio_write_32(ACPU_SC_VD_DLY_FIXED_CTRL, 0x1);
306 mmio_write_32(PMCTRL_ACPUPLLFREQ,
308 mmio_write_32(PMCTRL_ACPUPLLFRAC,
325 mmio_write_32(PMCTRL_ACPUVOLPMUADDR, 0x100da);
459 mmio_write_32(PMCTRL_ACPUPLLFREQ, acpu_dvfs_profile[tar_prof].acpu_pll_freq);
460 mmio_write_32(PMCTRL_ACPUPLLFRAC, acpu_dvfs_profile[tar_prof].acpu_pll_frac)
[all...] |
| hisi_ipc.c | 96 mmio_write_32(HISI_IPC_CPU_RAW_INT_ADDR, 1 << ipc_num);
116 mmio_write_32(HISI_IPC_ACPU_CTRL(signal), 0);
133 mmio_write_32(ACPU_CORE_POWERDOWN_FLAGS_ADDR, val);
163 mmio_write_32(ACPU_CLUSTER_POWERDOWN_FLAGS_ADDR, val);
189 mmio_write_32(ACPU_CORE_POWERDOWN_FLAGS_ADDR, val);
206 mmio_write_32(ACPU_CLUSTER_POWERDOWN_FLAGS_ADDR, val);
222 mmio_write_32(ACPU_CORE_POWERDOWN_FLAGS_ADDR, 0x8);
223 mmio_write_32(ACPU_CLUSTER_POWERDOWN_FLAGS_ADDR, 0x8);
|
| hisi_mcu.c | 155 mmio_write_32(AO_SC_PERIPH_CLKEN4,
160 mmio_write_32(PERI_SC_RESERVED8_ADDR, 0x0A001022);
163 mmio_write_32(AO_SC_PERIPH_RSTDIS4,
167 mmio_write_32(AO_SC_PERIPH_CLKEN4,
181 mmio_write_32((SOC_SRAM_M3_BASE_ADDR + 0x200), val);
185 mmio_write_32(AO_SC_MCU_SUBSYS_CTRL2, MCU_SYS_MEM_ADDR);
188 mmio_write_32(AO_SC_PERIPH_RSTDIS4,
195 mmio_write_32(AO_SC_SYS_CTRL2,
|
| /device/linaro/bootloader/arm-trusted-firmware/plat/juno/ |
| bl1_plat_setup.c | 130 mmio_write_32(SOC_NIC400_BASE +
132 mmio_write_32(SOC_NIC400_BASE +
134 mmio_write_32(SOC_NIC400_BASE +
136 mmio_write_32(SOC_NIC400_BASE +
138 mmio_write_32(SOC_NIC400_BASE +
140 mmio_write_32(SOC_NIC400_BASE +
148 mmio_write_32(CSS_NIC400_BASE +
163 mmio_write_32(PCIE_CONTROL_BASE + PCIE_SECURE_REG, PCIE_SEC_ACCESS_MASK);
180 mmio_write_32(SYS_CNTCTL_BASE + CNTCR_OFF, CNTCR_FCREQ(0) | CNTCR_EN);
|
| mhu.c | 71 mmio_write_32(MHU_BASE + CPU_INTR_S_SET, command);
89 mmio_write_32(MHU_BASE + SCP_INTR_S_CLEAR, 0xffffffffu);
102 mmio_write_32(MHU_BASE + CPU_INTR_S_CLEAR, 0xffffffffu);
|
| bl31_plat_setup.c | 166 mmio_write_32(SYS_CNTCTL_BASE + CNTCR_OFF, CNTCR_FCREQ(0) | CNTCR_EN);
172 mmio_write_32(SYS_TIMCTL_BASE + CNTACR_BASE(1), reg_val);
175 mmio_write_32(SYS_TIMCTL_BASE + CNTNSAR, reg_val);
|
| /device/linaro/bootloader/arm-trusted-firmware/plat/fvp/drivers/pwrc/ |
| fvp_pwrc.c | 57 mmio_write_32(PWRC_BASE + PSYSR_OFF, (unsigned int) mpidr);
66 mmio_write_32(PWRC_BASE + PPONR_OFF, (unsigned int) mpidr);
73 mmio_write_32(PWRC_BASE + PPOFFR_OFF, (unsigned int) mpidr);
80 mmio_write_32(PWRC_BASE + PWKUPR_OFF,
88 mmio_write_32(PWRC_BASE + PWKUPR_OFF,
96 mmio_write_32(PWRC_BASE + PCOFFR_OFF, (unsigned int) mpidr);
|
| /device/linaro/bootloader/arm-trusted-firmware/include/drivers/arm/ |
| gic_v2.h | 214 mmio_write_32(base + GICD_CTLR, val);
219 mmio_write_32(base + GICD_SGIR, val);
279 mmio_write_32(base + GICC_CTLR, val);
284 mmio_write_32(base + GICC_PMR, val);
289 mmio_write_32(base + GICC_BPR, val);
295 mmio_write_32(base + GICC_IAR, val);
300 mmio_write_32(base + GICC_EOIR, val);
305 mmio_write_32(base + GICC_HPPIR, val);
310 mmio_write_32(base + GICC_DIR, val);
|
| gic_v3.h | 81 mmio_write_32(base + GICR_WAKER, val);
|
| /device/linaro/bootloader/arm-trusted-firmware/plat/fvp/ |
| bl31_fvp_setup.c | 243 mmio_write_32(VE_SYSREGS_BASE + V2M_SYS_CFGDATA, 0);
244 mmio_write_32(VE_SYSREGS_BASE + V2M_SYS_CFGCTRL,
248 mmio_write_32(SYS_CNTCTL_BASE + CNTCR_OFF, CNTCR_FCREQ(0) | CNTCR_EN);
254 mmio_write_32(SYS_TIMCTL_BASE + CNTACR_BASE(0), reg_val);
255 mmio_write_32(SYS_TIMCTL_BASE + CNTACR_BASE(1), reg_val);
258 mmio_write_32(SYS_TIMCTL_BASE + CNTNSAR, reg_val);
|
| fvp_pm.c | 307 mmio_write_32(VE_SYSREGS_BASE + V2M_SYS_CFGCTRL,
317 mmio_write_32(VE_SYSREGS_BASE + V2M_SYS_CFGCTRL,
|
| /device/linaro/bootloader/arm-trusted-firmware/drivers/arm/gic/ |
| gic_v2.c | 120 mmio_write_32(base + GICD_IGROUPR + (n << 2), val);
126 mmio_write_32(base + GICD_ISENABLER + (n << 2), val);
132 mmio_write_32(base + GICD_ICENABLER + (n << 2), val);
138 mmio_write_32(base + GICD_ISPENDR + (n << 2), val);
144 mmio_write_32(base + GICD_ICPENDR + (n << 2), val);
150 mmio_write_32(base + GICD_ISACTIVER + (n << 2), val);
156 mmio_write_32(base + GICD_ICACTIVER + (n << 2), val);
162 mmio_write_32(base + GICD_IPRIORITYR + (n << 2), val);
168 mmio_write_32(base + GICD_ITARGETSR + (n << 2), val);
174 mmio_write_32(base + GICD_ICFGR + (n << 2), val)
[all...] |
| /device/linaro/bootloader/arm-trusted-firmware/drivers/arm/cci400/ |
| cci400.c | 88 mmio_write_32(get_slave_iface_base(mpidr) + SNOOP_CTRL_REG,
100 mmio_write_32(get_slave_iface_base(mpidr) + SNOOP_CTRL_REG,
|
| /device/linaro/bootloader/arm-trusted-firmware/drivers/arm/tzc400/ |
| tzc400.c | 65 mmio_write_32(base + GATE_KEEPER_OFF, val);
70 mmio_write_32(base + ACTION_OFF, action);
77 mmio_write_32(base + REGION_BASE_LOW_OFF +
85 mmio_write_32(base + REGION_BASE_HIGH_OFF +
93 mmio_write_32(base + REGION_TOP_LOW_OFF +
101 mmio_write_32(base + REGION_TOP_HIGH_OFF +
109 mmio_write_32(base + REGION_ATTRIBUTES_OFF +
117 mmio_write_32(base + REGION_ID_ACCESS_OFF +
|
| /device/linaro/bootloader/arm-trusted-firmware/include/lib/ |
| mmio.h | 54 static inline void mmio_write_32(uintptr_t addr, uint32_t value) function
|
