| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/mips/ |
| mips5-fp.l | 3 .*:62: Warning: condition code register should be even for movf.ps, was 3
|
| mipsr6@mips5-fp.l | 3 .*:5: Warning: condition code register should be even for movf.ps, was 3
|
| set-arch.l | 3 .*:147: Warning: condition code register should be even for movf.ps, was 3
|
| mips4-fp.s | 14 movf $4,$5,$fcc4
15 movf.d $f4,$f6,$fcc0
16 movf.s $f4,$f6,$fcc0
|
| mips4-fp.d | 21 [0-9a-f]+ <[^>]*> movf a0,a1,\$fcc4
22 [0-9a-f]+ <[^>]*> movf.d \$f4,\$f6,\$fcc0
23 [0-9a-f]+ <[^>]*> movf.s \$f4,\$f6,\$fcc0
|
| set-arch.s | 51 movf $4,$5,$fcc4
52 movf.d $f4,$f6,$fcc0
53 movf.s $f4,$f6,$fcc0
130 movf.ps $f26, $f28, $fcc2
147 movf.ps $f26, $f28, $fcc3 # warns
|
| micromips@mips4-fp.d | 26 [0-9a-f]+ <[^>]*> 5485 817b movf a0,a1,\$fcc4
27 [0-9a-f]+ <[^>]*> 5486 0220 movf\.d \$f4,\$f6,\$fcc0
28 [0-9a-f]+ <[^>]*> 5486 0020 movf\.s \$f4,\$f6,\$fcc0
|
| mips5-fp.s | 45 movf.ps $f26, $f28, $fcc2
62 movf.ps $f26, $f28, $fcc3 # warns
|
| mips5-fp.d | 51 0+00a4 <[^>]*> 46c8e691 movf\.ps \$f26,\$f28,\$fcc2
67 0+00e4 <[^>]*> 46cce691 movf\.ps \$f26,\$f28,\$fcc3
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/xstormy16/ |
| allinsn.s | 305 movf.b r0,(r0)
306 movf.w r7,(r15)
307 movf.w r4,(r8)
308 movf.b r3,(r7)
309 movf.w r1,(r1)
310 movf.b r6,(r15)
311 movf.b r1,(r10)
312 movf.b r6,(r1)
316 movf.b r0,(r0++)
317 movf.w r7,(r15++
[all...] |
| allinsn.sh | 344 movf.b r0,(r0)
345 movf.w r7,(r15)
346 movf.w r4,(r8)
347 movf.b r3,(r7)
348 movf.w r1,(r1)
349 movf.b r6,(r15)
350 movf.b r1,(r10)
351 movf.b r6,(r1)
355 movf.b r0,(r0++)
356 movf.w r7,(r15++
[all...] |
| allinsn.d | 280 248: 00 74 movf\.b r0,\(r0\)
281 24a: f7 75 movf\.w r7,\(r15\)
282 24c: 84 75 movf\.w r4,\(r8\)
283 24e: 73 74 movf\.b r3,\(r7\)
284 250: 11 75 movf\.w r1,\(r1\)
285 252: f6 74 movf\.b r6,\(r15\)
286 254: a1 74 movf\.b r1,\(r10\)
287 256: 16 74 movf\.b r6,\(r1\)
290 258: 00 64 movf\.b r0,\(r0\+\+\)
291 25a: f7 65 movf\.w r7,\(r15\+\+\
[all...] |
| /external/valgrind/none/tests/mips32/ |
| MoveIns.stdout.exp | 113 MOVF
114 movf $t0, $t1, $fcc0 :: out: 0x0, RDval: 0x0, RSval: 0xffffffff, cc: 1
115 movf $t0, $t1, $fcc0 :: out: 0xffffffff, RDval: 0xffffffff, RSval: 0xffffffff, cc: 0
116 movf $t0, $t1, $fcc0 :: out: 0x22b, RDval: 0x22b, RSval: 0xffffffff, cc: 1
117 movf $t0, $t1, $fcc0 :: out: 0x5, RDval: 0x0, RSval: 0x5, cc: 0
118 movf $t0, $t1, $fcc0 :: out: 0x0, RDval: 0x0, RSval: 0xffffffff, cc: 1
119 movf $t0, $t1, $fcc0 :: out: 0x19, RDval: 0xffffffff, RSval: 0x19, cc: 0
120 movf $t0, $t1, $fcc0 :: out: 0xffffffff, RDval: 0xffffffff, RSval: 0x0, cc: 1
121 movf $t0, $t1, $fcc0 :: out: 0x42, RDval: 0xffffffff, RSval: 0x42, cc: 0
122 movf $t0, $t1, $fcc4 :: out: 0xffffffff, RDval: 0x0, RSval: 0xffffffff, cc:
[all...] |
| /external/llvm/test/MC/Mips/ |
| micromips-movcond-instructions.s | 15 # CHECK-EL: movf $9, $6, $fcc0 # encoding: [0x26,0x55,0x7b,0x01]
22 # CHECK-EB: movf $9, $6, $fcc0 # encoding: [0x55,0x26,0x01,0x7b]
26 movf $9, $6, $fcc0
|
| mips-fpu-instructions.s | 163 # CHECK: movf $2, $1, $fcc0 # encoding: [0x01,0x10,0x20,0x00]
166 # CHECK: movf.d $f4, $f6, $fcc2 # encoding: [0x11,0x31,0x28,0x46]
167 # CHECK: movf.s $f4, $f6, $fcc5 # encoding: [0x11,0x31,0x14,0x46]
198 movf $2, $1, $fcc0
201 movf.d $f4, $f6, $fcc2
202 movf.s $f4, $f6, $fcc5
|
| /external/llvm/test/MC/Mips/mips3/ |
| invalid-mips4.s | 12 movf $gp,$8,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
13 movf $gp,$8,$fcc7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
14 movf.d $f6,$f11,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
15 movf.d $f6,$f11,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
16 movf.s $f23,$f5,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
17 movf.s $f23,$f5,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
|
| invalid-mips5.s | 13 movf $gp,$8,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
14 movf $gp,$8,$fcc7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
15 movf.d $f6,$f11,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
16 movf.d $f6,$f11,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
17 movf.s $f23,$f5,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
18 movf.s $f23,$f5,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
|
| /external/llvm/test/MC/Mips/mips2/ |
| invalid-mips32.s | 22 movf $gp,$8,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
23 movf $gp,$8,$fcc7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
24 movf.d $f6,$f11,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
25 movf.d $f6,$f11,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
26 movf.s $f23,$f5,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
27 movf.s $f23,$f5,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
|
| invalid-mips32r2.s | 31 movf $gp,$8,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
32 movf $gp,$8,$fcc7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
33 movf.d $f6,$f11,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
34 movf.d $f6,$f11,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
35 movf.s $f23,$f5,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
36 movf.s $f23,$f5,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
|
| invalid-mips4.s | 52 movf $gp,$8,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
53 movf $gp,$8,$fcc7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
54 movf.d $f6,$f11,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
55 movf.d $f6,$f11,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
56 movf.s $f23,$f5,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
57 movf.s $f23,$f5,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
|
| invalid-mips5.s | 50 movf $gp,$a0,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
51 movf $gp,$a0,$fcc7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
52 movf.d $f6,$f11,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
53 movf.d $f6,$f11,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
54 movf.s $f23,$f5,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
55 movf.s $f23,$f5,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
|
| /external/llvm/test/MC/Mips/mips32r6/ |
| invalid-mips32.s | 14 movf $gp,$8,$fcc7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
15 movf.d $f6,$f11,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
16 movf.s $f23,$f5,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/llvm/test/MC/Mips/mips64r6/ |
| invalid-mips64.s | 26 movf $gp,$8,$fcc7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
27 movf.d $f6,$f11,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
28 movf.s $f23,$f5,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/llvm/test/MC/Mips/mips1/ |
| invalid-mips4.s | 55 movf $gp,$8,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
56 movf $gp,$8,$fcc7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
57 movf.d $f6,$f10,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
58 movf.d $f6,$f10,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
59 movf.s $f23,$f5,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
60 movf.s $f23,$f5,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
|
| invalid-mips5.s | 54 movf $gp,$8,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
55 movf $gp,$8,$fcc7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
56 movf.d $f6,$f10,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
57 movf.d $f6,$f10,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
58 movf.s $f23,$f5,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
59 movf.s $f23,$f5,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
|
