| /external/llvm/test/MC/AArch64/ |
| elf-reloc-movw.s | 17 movn x17, #:abs_g0_s:some_label
20 movn x19, #:abs_g1_s:some_label
23 movn x19, #:abs_g2_s:some_label
|
| tls-relocs.s | 7 movn x2, #:dtprel_g2:var
9 movn x4, #:dtprel_g2:var
13 // CHECK: movn x2, #:dtprel_g2:var // encoding: [0bAAA00010,A,0b110AAAAA,0x92]
17 // CHECK: movn x4, #:dtprel_g2:var // encoding: [0bAAA00100,A,0b110AAAAA,0x92]
29 movn x6, #:dtprel_g1:var
31 movn w8, #:dtprel_g1:var
35 // CHECK: movn x6, #:dtprel_g1:var // encoding: [0bAAA00110,A,0b101AAAAA,0x92]
39 // CHECK: movn w8, #:dtprel_g1:var // encoding: [0bAAA01000,A,0b101AAAAA,0x12]
61 movn x12, #:dtprel_g0:var
63 movn w14, #:dtprel_g0:va
[all...] |
| arm64-tls-relocs.s | 44 movn x4, #:tprel_g2:var
47 // CHECK: movn x4, #:tprel_g2:var // encoding: [0bAAA00100,A,0b110AAAAA,0x92]
55 movn x6, #:tprel_g1:var
59 // CHECK: movn x6, #:tprel_g1:var // encoding: [0bAAA00110,A,0b101AAAAA,0x92]
81 movn x12, #:tprel_g0:var
85 // CHECK: movn x12, #:tprel_g0:var // encoding: [0bAAA01100,A,0b100AAAAA,0x92]
168 movn x4, #:dtprel_g2:var
171 // CHECK: movn x4, #:dtprel_g2:var // encoding: [0bAAA00100,A,0b110AAAAA,0x92]
179 movn x6, #:dtprel_g1:var
183 // CHECK: movn x6, #:dtprel_g1:var // encoding: [0bAAA00110,A,0b101AAAAA,0x92
[all...] |
| arm64-aliases.s | 166 movn x0, #0
167 movn x0, #0, lsl #16
168 movn x0, #0, lsl #32
169 movn x0, #0, lsl #48
170 movn w0, #0
171 movn w0, #0, lsl #16
173 ; CHECK: movn x0, #0x0, lsl #16
174 ; CHECK: movn x0, #0x0, lsl #32
175 ; CHECK: movn x0, #0x0, lsl #48
177 ; CHECK: movn w0, #0x0, lsl #1
[all...] |
| /toolchain/binutils/binutils-2.25/ld/testsuite/ld-aarch64/ |
| emit-relocs-272.d | 10 +1000c: 92c16747 movn x7, #0xb3a, lsl #32
12 +10010: 92c00011 movn x17, #0x0, lsl #32
|
| emit-relocs-270-bad.d | 13 +10010: 92802471 movn x17, #0x123
|
| emit-relocs-270.d | 12 +10010: 92802471 movn x17, #0x123
|
| emit-relocs-271.d | 12 +10010: 92a00011 movn x17, #0x0, lsl #16
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/mips/ |
| mips4.d | 9 0+0000 <[^>]*> movn a0,a2,a2
|
| mips4.s | 5 movn $4,$6,$6
|
| micromips@mips4.d | 10 [0-9a-f]+ <[^>]*> 00c6 2018 movn a0,a2,a2
|
| set-arch.s | 54 movn $4,$6,$6
55 movn.d $f4,$f6,$6
56 movn.s $f4,$f6,$6
131 movn.ps $f26, $f28, $3
|
| mips4-fp.s | 17 movn.d $f4,$f6,$6
18 movn.s $f4,$f6,$6
|
| mips4-fp.d | 24 [0-9a-f]+ <[^>]*> movn.d \$f4,\$f6,a2
25 [0-9a-f]+ <[^>]*> movn.s \$f4,\$f6,a2
|
| micromips@mips4-fp.d | 29 [0-9a-f]+ <[^>]*> 54c6 2138 movn\.d \$f4,\$f6,a2
30 [0-9a-f]+ <[^>]*> 54c6 2038 movn\.s \$f4,\$f6,a2
|
| /external/valgrind/none/tests/mips64/ |
| change_fp_mode.stdout.exp | 26 movn.s $f0, $f2, $t0 :: lo32(f1): 6b6b, lo32(f0): 90abcdef
27 movn.s $f0, $f1, $t0 :: lo32(f1): 6b6b, lo32(f0): 6b6b
28 movn.s $f1, $f2, $t0 :: lo32(f1): 90abcdef, lo32(f0): 5a5a
29 movn.s $f0, $f2, $0 :: lo32(f1): 6b6b, lo32(f0): 5a5a
30 movn.s $f0, $f1, $0 :: lo32(f1): 6b6b, lo32(f0): 5a5a
31 movn.s $f1, $f2, $0 :: lo32(f1): 6b6b, lo32(f0): 5a5a
32 movn.d $f0, $f2, $t0 :: lo32(f1): 6b6b, lo32(f0): 90abcdef
33 movn.d $f0, $f1, $t0 :: lo32(f1): 6b6b, lo32(f0): 6b6b
34 movn.d $f1, $f2, $t0 :: lo32(f1): 90abcdef, lo32(f0): 5a5a
35 movn.d $f0, $f2, $0 :: lo32(f1): 6b6b, lo32(f0): 5a5
[all...] |
| /external/llvm/test/MC/Mips/ |
| micromips-movcond-instructions.s | 13 # CHECK-EL: movn $9, $6, $7 # encoding: [0xe6,0x00,0x18,0x48]
20 # CHECK-EB: movn $9, $6, $7 # encoding: [0x00,0xe6,0x48,0x18]
24 movn $9, $6, $7
|
| /external/llvm/test/MC/Mips/mips3/ |
| invalid-mips4.s | 18 movn $v1,$s1,$s0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
19 movn.d $f27,$f21,$k0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
20 movn.s $f12,$f0,$s7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| invalid-mips5.s | 19 movn $v1,$s1,$s0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
20 movn.d $f27,$f21,$k0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
21 movn.s $f12,$f0,$s7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/llvm/test/MC/Mips/mips32r6/ |
| invalid-mips32.s | 17 movn $v1,$s1,$s0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
18 movn.d $f27,$f21,$k0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
19 movn.s $f12,$f0,$s7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/aarch64/ |
| mov-no-aliases.d | 18 24: 12800000 movn w0, #0x0
|
| /external/valgrind/none/tests/mips32/ |
| MoveIns.stdout.exp | 192 MOVN.S
193 movn.s $f0, $f2, $t3 :: fs rt 0x0
194 movn.s $f0, $f2, $t3 :: fs rt 0x43e41fde
195 movn.s $f0, $f2, $t3 :: fs rt 0x40400000
196 movn.s $f0, $f2, $t3 :: fs rt 0xbf800000
197 movn.s $f0, $f2, $t3 :: fs rt 0x44ad1333
198 movn.s $f0, $f2, $t3 :: fs rt 0x0
199 movn.s $f0, $f2, $t3 :: fs rt 0x0
200 movn.s $f0, $f2, $t3 :: fs rt 0xc5b4d3c3
201 movn.s $f0, $f2, $t3 :: fs rt 0x44db000
[all...] |
| /frameworks/native/opengl/libagl/arch-mips/ |
| fixed_asm.S | 50 movn $v0,$t2,$t0 /* if negative? */
|
| /system/core/libpixelflinger/arch-mips/ |
| t32cb16blend.S | 86 DBG movn $v0,$t8,$at
88 DBG movn $v1,$t8,$at
173 DBG movn $v0,$t8,$at
175 DBG movn $v1,$t8,$at
|
| /external/libmpeg2/common/armv8/ |
| ideint_spatial_filter_av8.s | 169 movn x11, #0
198 movn x11, #0
|
