| /external/mesa3d/src/gallium/drivers/vc4/ |
| vc4_nir_lower_txf_ms.c | 86 nir_ssa_def *x_tile = nir_ushr(b, x, nir_imm_int(b, tile_w_shift));
87 nir_ssa_def *y_tile = nir_ushr(b, y, nir_imm_int(b, tile_h_shift));
90 nir_imm_int(b, tile_size)),
92 nir_imm_int(b, (w_tiles *
95 nir_imm_int(b, (tile_w - 1) & ~1));
97 nir_imm_int(b, (tile_h - 1) & ~1));
100 nir_imm_int(b, 2 * VC4_MAX_SAMPLES * sizeof(uint32_t))),
102 nir_imm_int(b,
110 nir_imm_int(b, 2)),
111 nir_imm_int(b, (1 << 2)))
[all...] |
| vc4_nir_lower_io.c | 60 nir_imm_int(b, 8 * chan),
61 nir_imm_int(b, 8));
70 nir_imm_int(b, 16 * chan),
71 nir_imm_int(b, 16));
79 return nir_iand(b, src, nir_imm_int(b, 0xffff));
81 return nir_ushr(b, src, nir_imm_int(b, 16));
120 temp = nir_ixor(b, vpm, nir_imm_int(b, 0x80808080));
198 intr_comp->src[0] = nir_src_for_ssa(nir_imm_int(b, 0));
345 nir_imm_int(b, 4)));
|
| vc4_nir_lower_blend.c | 64 load->src[0] = nir_src_for_ssa(nir_imm_int(b, 0));
173 nir_iand(b, src0, nir_imm_int(b, ~chan_mask)),
174 nir_iand(b, src1, nir_imm_int(b, chan_mask)));
188 return nir_imm_int(b, ~0);
202 nir_imm_int(b, ~0),
209 return nir_imm_int(b, 0);
232 return nir_imm_int(b, ~0);
326 nir_ssa_def *or1 = nir_ior(b, src, nir_ishl(b, src, nir_imm_int(b, 8)));
327 return nir_ior(b, or1, nir_ishl(b, or1, nir_imm_int(b, 16)));
342 nir_ssa_def *imm_0xff = nir_imm_int(b, 0xff)
[all...] |
| /external/mesa3d/src/compiler/nir/ |
| nir_lower_double_ops.c | 50 nir_ssa_def *new_hi = nir_bfi(b, nir_imm_int(b, 0x7ff00000), exp, hi);
62 return nir_ubitfield_extract(b, hi, nir_imm_int(b, 20), nir_imm_int(b, 11));
78 nir_ssa_def *inf_hi = nir_ior(b, nir_imm_int(b, 0x7ff00000), zero_hi);
79 return nir_pack_double_2x32_split(b, nir_imm_int(b, 0), inf_hi);
97 res = nir_bcsel(b, nir_ior(b, nir_ige(b, nir_imm_int(b, 0), exp),
114 nir_ssa_def *src_norm = set_exponent(b, src, nir_imm_int(b, 1023));
126 nir_imm_int(b, 1023)));
175 nir_imm_int(b, 1023));
176 nir_ssa_def *even = nir_iand(b, unbiased_exp, nir_imm_int(b, 1))
[all...] |
| nir_lower_patch_vertices.c | 41 nir_ssa_def *val = nir_imm_int(&b, patch_vertices);
|
| nir_lower_gs_intrinsics.c | 80 nir_imm_int(b, b->shader->info->gs.vertices_out);
103 nir_iadd(b, count, nir_imm_int(b, 1)),
204 nir_store_var(&b, state.vertex_count_var, nir_imm_int(&b, 0), 0x1);
|
| nir_lower_alu_to_scalar.c | 146 nir_extract_u16(b, instr->src[0].src.ssa, nir_imm_int(b, 0));
148 nir_ior(b, nir_ishl(b, nir_channel(b, word, 1), nir_imm_int(b, 16)),
161 nir_extract_u8(b, instr->src[0].src.ssa, nir_imm_int(b, 0));
163 nir_ior(b, nir_ior(b, nir_ishl(b, nir_channel(b, byte, 3), nir_imm_int(b, 24)),
164 nir_ishl(b, nir_channel(b, byte, 2), nir_imm_int(b, 16))),
165 nir_ior(b, nir_ishl(b, nir_channel(b, byte, 1), nir_imm_int(b, 8)),
|
| nir_lower_system_values.c | 91 nir_imm_int(b, b->shader->info->cs.local_size[0]);
93 nir_imm_int(b, b->shader->info->cs.local_size[1]);
|
| nir_lower_idiv.c | 74 bf = nir_isub(bld, bf, nir_imm_int(bld, 2)); /* yes, really */
104 r = nir_ishr(bld, r, nir_imm_int(bld, 31));
|
| nir_lower_samplers.c | 58 nir_imul(b, nir_imm_int(b, *array_elements),
110 indirect = nir_umin(b, indirect, nir_imm_int(b, array_elements - 1));
|
| nir_lower_io.c | 102 nir_ssa_def *vtx = nir_imm_int(b, deref_array->base_offset);
119 return nir_imm_int(b, type_size(glsl_vec4_type()) * slot_offset);
123 nir_ssa_def *offset = nir_imm_int(b, 0);
134 nir_imm_int(b, size * deref_array->base_offset));
138 nir_imul(b, nir_imm_int(b, size),
150 offset = nir_iadd(b, offset, nir_imm_int(b, field_offset));
|
| nir_lower_clip.c | 78 store->src[1] = nir_src_for_ssa(nir_imm_int(b, 0));
90 load->src[0] = nir_src_for_ssa(nir_imm_int(b, 0));
|
| nir_lower_returns.c | 192 nir_store_var(b, state->return_flag, nir_imm_int(b, NIR_FALSE), 1);
196 nir_store_var(b, state->return_flag, nir_imm_int(b, NIR_TRUE), 1);
|
| nir_lower_two_sided_color.c | 75 load->src[0] = nir_src_for_ssa(nir_imm_int(b, 0));
|
| nir_lower_indirect_derefs.c | 60 nir_imm_int(b, mid)));
|
| /external/mesa3d/src/mesa/drivers/dri/i965/ |
| brw_nir_tcs_workarounds.c | 82 load->src[0] = nir_src_for_ssa(nir_imm_int(b, 0));
119 store->src[1] = nir_src_for_ssa(nir_imm_int(b, 0));
|
| brw_nir_intrinsics.c | 51 return nir_imm_int(b, 0);
60 load->src[0] = nir_src_for_ssa(nir_imm_int(b, 0));
|
| /external/mesa3d/src/intel/blorp/ |
| blorp_blit.c | 210 tex->src[1].src = nir_src_for_ssa(nir_imm_int(b, 0));
226 tex->src[1].src = nir_src_for_ssa(nir_imm_int(b, 0));
245 tex->src[1].src = nir_src_for_ssa(nir_imm_int(b, 0));
279 nir_ssa_def *masked = nir_iand(b, src, nir_imm_int(b, src_mask));
283 shifted = nir_ishl(b, masked, nir_imm_int(b, src_left_shift));
285 shifted = nir_ushr(b, masked, nir_imm_int(b, -src_left_shift));
337 nir_ssa_def *x_W = nir_imm_int(b, 0);
342 nir_ssa_def *y_W = nir_imm_int(b, 0);
372 nir_ssa_def *x_Y = nir_imm_int(b, 0);
378 nir_ssa_def *y_Y = nir_imm_int(b, 0)
[all...] |
| /external/mesa3d/src/amd/vulkan/ |
| radv_meta_buffer.c | 27 nir_ssa_def *offset = nir_imul(&b, global_id, nir_imm_int(&b, 16));
32 dst_buf->src[0] = nir_src_for_ssa(nir_imm_int(&b, 0));
39 load->src[0] = nir_src_for_ssa(nir_imm_int(&b, 0));
77 nir_ssa_def *offset = nir_imul(&b, global_id, nir_imm_int(&b, 16));
82 dst_buf->src[0] = nir_src_for_ssa(nir_imm_int(&b, 0));
90 src_buf->src[0] = nir_src_for_ssa(nir_imm_int(&b, 0));
|
| radv_meta_resolve_cs.c | 74 src_offset->src[0] = nir_src_for_ssa(nir_imm_int(&b, 0));
80 dst_offset->src[0] = nir_src_for_ssa(nir_imm_int(&b, 8));
95 tex->src[1].src = nir_src_for_ssa(nir_imm_int(&b, 0));
124 nir_ssa_def *all_same = nir_ine(&b, &tex_all_same->dest.ssa, nir_imm_int(&b, 0));
137 tex_add->src[1].src = nir_src_for_ssa(nir_imm_int(&b, i));
|
| radv_meta_bufimage.c | 71 offset->src[0] = nir_src_for_ssa(nir_imm_int(&b, 0));
77 stride->src[0] = nir_src_for_ssa(nir_imm_int(&b, 8));
90 tex->src[1].src = nir_src_for_ssa(nir_imm_int(&b, 0));
266 offset->src[0] = nir_src_for_ssa(nir_imm_int(&b, 0));
272 stride->src[0] = nir_src_for_ssa(nir_imm_int(&b, 8));
293 tex->src[1].src = nir_src_for_ssa(nir_imm_int(&b, 0));
461 src_offset->src[0] = nir_src_for_ssa(nir_imm_int(&b, 0));
467 dst_offset->src[0] = nir_src_for_ssa(nir_imm_int(&b, 8));
482 tex->src[1].src = nir_src_for_ssa(nir_imm_int(&b, 0));
642 clear_val->src[0] = nir_src_for_ssa(nir_imm_int(&b, 0))
[all...] |
| /external/mesa3d/src/compiler/spirv/ |
| vtn_variables.c | 56 return nir_imm_int(&b->nb, link.id * stride);
61 nir_imm_int(&b->nb, stride));
316 array_index = nir_imm_int(&b->nb, 0);
344 nir_ssa_def *offset = nir_imm_int(&b->nb, 0);
370 nir_imm_int(&b->nb, type->offsets[member]));
494 nir_imm_int(&b->nb, access_offset)));
509 (*inout)->def = nir_ine(&b->nb, (*inout)->def, nir_imm_int(&b->nb, 0));
559 nir_imm_int(&b->nb, i * type->stride));
596 nir_imm_int(&b->nb, i * type->stride));
651 nir_iadd(&b->nb, offset, nir_imm_int(&b->nb, i * type->stride))
[all...] |
| vtn_cfg.c | 549 nir_store_var(&b->nb, switch_fall_var, nir_imm_int(&b->nb, NIR_FALSE), 1);
676 nir_store_var(&b->nb, do_cont, nir_imm_int(&b->nb, NIR_FALSE), 1);
687 nir_store_var(&b->nb, do_cont, nir_imm_int(&b->nb, NIR_TRUE), 1);
705 nir_store_var(&b->nb, fall_var, nir_imm_int(&b->nb, NIR_FALSE), 1);
728 nir_ieq(&b->nb, sel, nir_imm_int(&b->nb, *val));
756 nir_store_var(&b->nb, fall_var, nir_imm_int(&b->nb, NIR_TRUE), 1);
|
| /external/mesa3d/src/intel/vulkan/ |
| anv_nir_apply_pipeline_layout.c | 122 block_index = nir_umin(b, block_index, nir_imm_int(b, array_size - 1));
124 block_index = nir_iadd(b, nir_imm_int(b, surface_index), block_index);
145 nir_iadd(b, nir_imm_int(b, deref_array->base_offset),
149 index = nir_umin(b, index, nir_imm_int(b, array_size - 1));
|
| anv_nir_lower_input_attachments.c | 99 tex->src[1].src = nir_src_for_ssa(nir_imm_int(&b, 0));
|
