| /external/mesa3d/src/gallium/drivers/vc4/ |
| vc4_nir_lower_txf_ms.c | 109 nir_ishl(b, x,
113 nir_ishl(b, y,
117 nir_ssa_def *sample_addr = nir_ishl(b, sample_index, nir_imm_int(b, 4));
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| vc4_nir_lower_io.c | 344 nir_src_for_ssa(nir_ishl(b, intr->src[0].ssa,
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| vc4_nir_lower_blend.c | 326 nir_ssa_def *or1 = nir_ior(b, src, nir_ishl(b, src, nir_imm_int(b, 8)));
327 return nir_ior(b, or1, nir_ishl(b, or1, nir_imm_int(b, 16)));
653 nir_ishl(b,
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| /external/mesa3d/src/compiler/nir/ |
| nir_lower_alu_to_scalar.c | 148 nir_ior(b, nir_ishl(b, nir_channel(b, word, 1), nir_imm_int(b, 16)),
163 nir_ior(b, nir_ior(b, nir_ishl(b, nir_channel(b, byte, 3), nir_imm_int(b, 24)),
164 nir_ishl(b, nir_channel(b, byte, 2), nir_imm_int(b, 16))),
165 nir_ior(b, nir_ishl(b, nir_channel(b, byte, 1), nir_imm_int(b, 8)),
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| nir_lower_double_ops.c | 330 nir_ishl(b, nir_imm_int(b, ~0), frac_bits));
336 nir_ishl(b,
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| /external/mesa3d/src/mesa/drivers/dri/i965/ |
| brw_nir_attribute_workarounds.c | 80 val = nir_ishr(b, nir_ishl(b, val, shift), shift);
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| /external/mesa3d/src/intel/blorp/ |
| blorp_blit.c | 283 shifted = nir_ishl(b, masked, nir_imm_int(b, src_left_shift));
829 nir_ishl(b, sample, nir_imm_int(b, 2))),
834 nir_ishl(b, sample, nir_imm_int(b, 2))),
838 nir_ishl(b, nir_iadd(b, sample,
[all...] |
| /external/mesa3d/prebuilt-intermediates/nir/ |
| nir_builder_opcodes.h | 684 nir_ishl(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1) function
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| /external/mesa3d/src/compiler/glsl/ |
| glsl_to_nir.cpp | [all...] |
| /external/mesa3d/src/gallium/auxiliary/nir/ |
| tgsi_to_nir.c | 662 offset = nir_ishl(b, offset, nir_imm_int(b, 4));
[all...] |
