| /external/compiler-rt/lib/builtins/arm/ |
| sync_fetch_and_or_8.S | 19 orr rD_LO, rN_LO, rM_LO ; \
20 orr rD_HI, rN_HI, rM_HI
|
| sync_fetch_and_or_4.S | 17 #define or_4(rD, rN, rM) orr rD, rN, rM
|
| /art/runtime/interpreter/mterp/arm64/ |
| op_const_wide.S | 9 orr w0, w0, w1, lsl #16 // w0<- BBBBbbbb
10 orr x0, x0, x2, lsl #32 // w0<- hhhhBBBBbbbb
11 orr x0, x0, x3, lsl #48 // w0<- HHHHhhhhBBBBbbbb
|
| op_goto_32.S | 15 orr wINST, w0, w1, lsl #16 // wINST<- AAAAaaaa
|
| op_const.S | 6 orr w0, w0, w1, lsl #16 // w0<- BBBBbbbb
|
| op_const_wide_32.S | 7 orr x0, x0, x2, lsl #16 // x0<- ssssssssBBBBbbbb
|
| op_packed_switch.S | 15 orr x0, x0, x1, lsl #16 // x0<- ssssssssBBBBbbbb
|
| op_const_string_jumbo.S | 6 orr w0, w0, w2, lsl #16 // w1<- BBBBbbbb
|
| op_fill_array_data.S | 6 orr x1, x0, x1, lsl #16 // x1<- ssssssssBBBBbbbb
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/aarch64/ |
| rm-simd-ext.s | 27 orr v0.16b, v1.16b, v2.16b
28 orr w1, w1, w3
|
| rm-simd-ext.l | 2 [^:]*:27: Error: selected processor does not support `orr v0.16b,v1.16b,v2.16b'
|
| mov-no-aliases.d | 15 18: aa0f03e7 orr x7, xzr, x15
16 1c: 2a0f03e7 orr w7, wzr, w15
19 28: b2607fe0 orr x0, xzr, #0xffffffff00000000
20 2c: b2400fff orr sp, xzr, #0xf
21 30: 32000fff orr wsp, wzr, #0xf
27 48: 320de400 orr w0, w0, #0x99999999
|
| /external/llvm/test/MC/AArch64/ |
| neon-mov.s | 102 orr v0.2s, #1
103 orr v1.2s, #0
104 orr v0.2s, #1, lsl #8
105 orr v0.2s, #1, lsl #16
106 orr v0.2s, #1, lsl #24
107 orr v0.4s, #1
108 orr v0.4s, #1, lsl #8
109 orr v0.4s, #1, lsl #16
110 orr v0.4s, #1, lsl #24
111 orr v31.4h, #
[all...] |
| alias-logicalimm.s | 23 // CHECK: orr x0, x1, #0xfffffffffffffffd
24 // CHECK: orr x0, x1, #0xfffffffffffffffd
25 orr x0, x1, #~2
28 // CHECK: orr w2, w1, #0xfffffffc
29 // CHECK: orr w2, w1, #0xfffffffc
30 orr w2, w1, #~3
|
| arm64-aliases.s | 25 ; ORR Rd, Rn, Rn is a MOV
27 orr x2, xzr, x9
29 orr w2, wzr, w9
190 orr x20, xzr, #0xaaaaaaaaaaaaaaaa
191 orr w15, wzr, #0xaaaaaaaa
195 ; ORR is mostly repeating bit sequences and cannot encode -1, so it only
198 orr x3, xzr, #0x1
199 orr w3, wzr, #0x1
200 orr x3, xzr, #0x10000
201 orr w3, wzr, #0x1000
[all...] |
| /device/linaro/bootloader/edk2/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressSecLibRTSM/AArch64/ |
| GicV3.S | 39 orr x0, x0, #1
45 orr x1, x1, x0
51 orr x1, x1, x0
|
| /device/linaro/bootloader/edk2/ArmPlatformPkg/ArmVExpressPkg/Scripts/uefi-aarch64-bootstrap/ |
| boot.S | 60 orr x0, x0, #(1 << 0) // Non-secure bit
61 orr x0, x0, #(1 << 8) // HVC enable
62 orr x0, x0, #(1 << 10) // 64-bit EL2
91 orr w0, w0, #3 // EnableGrp0 | EnableGrp1
103 orr x0, x0, #(1 << 31) // Set EL1 to be 64bit
115 orr x0, x0, #3 // Enable EL1 access to timers
119 orr x0, x0, #3 // EL0 access to counters
148 orr w5, w5, #0x0001 // cr
|
| /device/linaro/bootloader/arm-trusted-firmware/plat/hikey/drivers/ |
| hisi_pwrc_sram.S | 48 orr x0, x0, #0x180000
49 orr x0, x0, #0xe000
53 orr x3, x3, #(0x1<<5)
57 orr x3, x3, #(0x1<<5)
|
| /bionic/libc/arch-arm/generic/bionic/ |
| memcpy.S | 250 orr r4, r3, r5, lsl lr
278 orr r3, r3, r4, lsl #16
280 orr r4, r4, r5, lsl #16
282 orr r5, r5, r6, lsl #16
284 orr r6, r6, r7, lsl #16
286 orr r7, r7, r8, lsl #16
288 orr r8, r8, r9, lsl #16
290 orr r9, r9, r10, lsl #16
292 orr r10, r10, r11, lsl #16
305 orr r3, r3, r4, lsl #2
[all...] |
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/arm/ |
| tcompat2.s | 21 orr r0,r0,r1
22 orr r0,r1,r0
|
| /bionic/libc/arch-arm64/generic/bionic/ |
| strlen.S | 112 orr tmp2, data1, REP8_7f
114 orr tmp4, data2, REP8_7f
141 orr tmp2, tmp1, tmp3
147 orr tmp2, tmp1, tmp3
153 orr tmp2, data1, REP8_7f
154 orr tmp4, data2, REP8_7f
170 orr tmp2, data1, REP8_7f
186 orr tmp2, data1, REP8_7f
188 orr tmp4, data2, REP8_7f
195 orr tmp2, data1, REP8_7
[all...] |
| strnlen.S | 94 orr tmp2, data1, #REP8_7f
96 orr tmp4, data2, #REP8_7f
100 orr tmp1, has_nul1, has_nul2
105 orr tmp1, has_nul1, has_nul2
127 orr tmp2, data2, #REP8_7f
168 orr data1, data1, tmp2
169 orr data2a, data2, tmp2
|
| /device/linaro/bootloader/edk2/ArmPlatformPkg/PrePeiCore/AArch64/ |
| Helper.S | 39 orr x0, x0, #(1 << 3) // Enable EL2 FIQ
40 orr x0, x0, #(1 << 4) // Enable EL2 IRQ
41 orr x0, x0, #(1 << 5) // Enable EL2 SError and Abort
|
| /system/core/libpixelflinger/arch-arm64/ |
| t32cb16blend.S | 75 orr w17, \FB, #(0x1F<<(16 + 11))
76 orr w18, \FB, w16, lsl #(16 + 11)
86 orr w17, \FB, #(0x3F<<(16 + 5))
87 orr w18, \FB, w6, lsl #(16 + 5)
97 orr w17, \FB, #(0x1F << 16)
98 orr w18, \FB, w16, lsl #16
123 orr w17, \FB, #(0x3F<<5)
124 orr w18, \FB, w6, lsl #5
134 orr w17, \FB, #0x1F
135 orr w18, \FB, w1
[all...] |
| /device/linaro/bootloader/edk2/ArmPlatformPkg/Sec/AArch64/ |
| Helper.S | 31 orr x0, x0, #(1 << 31) // Set EL1 to be 64bit
43 orr x0, x0, #3 // Enable EL1 access to timers
47 orr x0, x0, #3 // EL0 access to counters
82 orr x0, x0, x1
84 orr x0, x0, x1
|
