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    Searched refs:prev_inst (Results 1 - 6 of 6) sorted by null

  /external/mesa3d/src/mesa/drivers/dri/i965/
brw_dead_control_flow.cpp 50 backend_instruction *const prev_inst = prev_block->end(); local
56 prev_inst->opcode == BRW_OPCODE_ELSE) {
58 backend_instruction *const else_inst = prev_inst;
63 prev_inst->opcode == BRW_OPCODE_IF) {
67 backend_instruction *const if_inst = prev_inst;
100 prev_inst->opcode == BRW_OPCODE_IF) {
102 backend_instruction *const if_inst = prev_inst;
brw_vec4_reg_allocate.cpp 316 for (vec4_instruction *prev_inst = (vec4_instruction *) inst->prev;
317 !prev_inst->is_head_sentinel();
318 prev_inst = (vec4_instruction *) prev_inst->prev) {
324 if (prev_inst->dst.file == VGRF && prev_inst->dst.nr == scratch_reg) {
325 return (!prev_inst->predicate || prev_inst->opcode == BRW_OPCODE_SEL) &&
327 ~prev_inst->dst.writemask) == 0;
334 if (prev_inst->opcode == SHADER_OPCODE_GEN4_SCRATCH_WRITE |
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brw_fs.cpp     [all...]
  /toolchain/binutils/binutils-2.25/opcodes/
microblaze-dis.c 206 unsigned long inst, prev_inst; local
224 prev_inst = read_insn_microblaze (prev_insn_addr, info, &pop);
225 if (prev_inst == 0)
229 immval = (get_int_field_imm (prev_inst) << 16) & 0xffff0000;
  /external/mesa3d/src/gallium/drivers/vc4/
vc4_qpu_schedule.c 573 struct schedule_node *prev_inst)
581 if (prev_inst) {
582 uint32_t prev_sig = QPU_GET_FIELD(prev_inst->inst->inst,
622 if (prev_inst) {
631 if (prev_inst->uniform != -1 && n->uniform != -1)
642 inst = qpu_merge_inst(prev_inst->inst->inst, inst);
    [all...]
  /art/runtime/verifier/
method_verifier.cc 2341 const Instruction* prev_inst = Instruction::At(code_item_->insns_ + prev_idx); local
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