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  /external/libavc/common/armv8/
ih264_neon_macros.s 36 .macro swp reg1, reg2
37 eor \reg1, \reg1, \reg2
38 eor \reg2, \reg1, \reg2
39 eor \reg1, \reg1, \reg2
  /external/libmpeg2/common/armv8/
impeg2_neon_macros.s 53 .macro swp reg1, reg2
54 eor \reg1, \reg1, \reg2
55 eor \reg2, \reg1, \reg2
56 eor \reg1, \reg1, \reg2
  /external/llvm/test/MC/MachO/
bad-macro.s 5 .macro test_macro reg1, reg2
  /external/libvpx/libvpx/vpx_dsp/mips/
idct32x32_msa.c 44 v8i16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; local
48 LD_SH8(tmp_buf, 32, reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7);
59 DOTP_CONST_PAIR(reg2, reg6, cospi_24_64, cospi_8_64, reg2, reg6);
60 BUTTERFLY_4(reg4, reg0, reg2, reg6, vec1, vec3, vec2, vec0);
65 LD_SH8((tmp_buf + 16), 32, reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7);
68 DOTP_CONST_PAIR(reg2, reg5, cospi_22_64, cospi_10_64, reg2, reg5);
73 reg4 = reg6 + reg2;
74 reg6 = reg6 - reg2;
128 v8i16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; local
354 v8i16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; local
434 v8i16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; local
    [all...]
idct16x16_msa.c 15 v8i16 reg0, reg2, reg4, reg6, reg8, reg10, reg12, reg14; local
19 LD_SH8(input, 16, reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7);
23 TRANSPOSE8x8_SH_SH(reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg0, reg1,
24 reg2, reg3, reg4, reg5, reg6, reg7);
27 DOTP_CONST_PAIR(reg2, reg14, cospi_28_64, cospi_4_64, reg2, reg14);
29 BUTTERFLY_4(reg2, reg14, reg6, reg10, loc0, loc1, reg14, reg2);
30 DOTP_CONST_PAIR(reg14, reg2, cospi_16_64, cospi_16_64, loc2, loc3);
33 BUTTERFLY_4(reg8, reg0, reg4, reg12, reg2, reg6, reg10, reg14)
109 v8i16 reg0, reg2, reg4, reg6, reg8, reg10, reg12, reg14; local
    [all...]
  /art/runtime/interpreter/mterp/arm64/
header.S 299 .macro SAVE_TWO_REGS reg1, reg2, offset
300 stp \reg1, \reg2, [sp, #(\offset)]
302 .cfi_rel_offset \reg2, (\offset) + 8
308 .macro RESTORE_TWO_REGS reg1, reg2, offset
309 ldp \reg1, \reg2, [sp, #(\offset)]
311 .cfi_restore \reg2
317 .macro SAVE_TWO_REGS_INCREASE_FRAME reg1, reg2, frame_adjustment
318 stp \reg1, \reg2, [sp, #-(\frame_adjustment)]!
321 .cfi_rel_offset \reg2, 8
327 .macro RESTORE_TWO_REGS_DECREASE_FRAME reg1, reg2, frame_adjustmen
    [all...]
  /device/linaro/bootloader/arm-trusted-firmware/bl32/tsp/aarch64/
tsp_entrypoint.S 56 .macro save_eret_context reg1 reg2
58 mrs \reg2, spsr_el1
59 stp \reg1, \reg2, [sp, #-0x10]!
63 .macro restore_eret_context reg1 reg2
65 ldp \reg1, \reg2, [sp], #0x10
67 msr spsr_el1, \reg2
  /external/libunwind/src/ptrace/
_UPT_access_mem.c 63 long reg1, reg2;
67 reg2 = ptrace (PTRACE_PEEKDATA, pid, (void*) (uintptr_t) (addr + sizeof(long)), 0);
70 *val = ((unw_word_t)(reg2) << 32) | (uint32_t) reg1;
  /external/boringssl/src/crypto/perlasm/
x86gas.pl 77 { my($addr,$reg1,$reg2,$idx)=@_;
80 if (!defined($idx) && 1*$reg2) { $idx=$reg2; $reg2=$reg1; undef $reg1; }
87 $reg2 = "%$reg2" if ($reg2);
91 if ($reg2)
93 $ret .= "($reg1,$reg2,$idx)";
x86masm.pl 46 { my($size,$addr,$reg1,$reg2,$idx)=@_;
49 if (!defined($idx) && 1*$reg2) { $idx=$reg2; $reg2=$reg1; undef $reg1; }
65 if ($reg2 ne "")
67 $ret .= "$reg2*$idx";
x86nasm.pl 43 { my($size,$addr,$reg1,$reg2,$idx)=@_;
46 if (!defined($idx) && 1*$reg2) { $idx=$reg2; $reg2=$reg1; undef $reg1; }
66 if ($reg2 ne "")
68 $ret .= "$reg2*$idx";
  /toolchain/binutils/binutils-2.25/gas/config/
tc-microblaze.c 895 unsigned reg2; local
946 op_end = parse_reg (op_end + 1, &reg2); /* Get r1. */
950 reg2 = 0;
963 if (check_spl_reg (& reg2))
973 inst |= (reg2 << RB_LOW) & RB_MASK;
978 inst |= (reg2 << RA_LOW) & RA_MASK;
993 op_end = parse_reg (op_end + 1, &reg2); /* Get r1. */
997 reg2 = 0;
1007 if (check_spl_reg (& reg2))
1020 if (reg2 == REG_ROSDP
    [all...]
  /external/webrtc/webrtc/system_wrappers/include/
asm_defines.h 59 .macro streqh reg1, reg2, num variable
60 strheq \reg1, \reg2, \num variable
  /external/v8/src/interpreter/
bytecode-register.cc 107 bool Register::AreContiguous(Register reg1, Register reg2, Register reg3,
109 if (reg1.index() + 1 != reg2.index()) {
112 if (reg3.is_valid() && reg2.index() + 1 != reg3.index()) {
  /toolchain/binutils/binutils-2.25/opcodes/
i960-dis.c 325 const char *reg1, *reg2, *reg3;
401 reg2 = reg_names[ (word1 >> 14) & 0x1f ];
410 ea (memaddr, mode, reg2, reg3, word1, word2);
418 (*info->fprintf_func) (stream, "(%s)", reg2);
429 ea (memaddr, mode, reg2, reg3, word1, word2);
437 (*info->fprintf_func) (stream, "(%s)", reg2);
445 ea (memaddr, mode, reg2, reg3, word1, word2);
452 (*info->fprintf_func) (stream, "(%s)", reg2);
767 ea (bfd_vma memaddr, int mode, const char *reg2, const char *reg3, int word1,
785 (*info->fprintf_func)( stream, "(%s)", reg2 );
324 const char *reg1, *reg2, *reg3; local
    [all...]
  /external/libyuv/files/source/
row_msa.cc 481 v16u8 reg0, reg1, reg2, reg3; local
507 reg2 = (v16u8)__msa_ilvev_b((v16i8)vec4, (v16i8)vec3);
509 reg1 = (v16u8)__msa_sldi_b((v16i8)reg2, (v16i8)reg0, 11);
512 dst2 = (v16u8)__msa_vshf_b(shuffler2, (v16i8)reg3, (v16i8)reg2);
570 v8u16 reg0, reg1, reg2; local
587 reg2 = (v8u16)__msa_srai_h(vec2, 4);
589 reg2 = (v8u16)__msa_slli_h((v8i16)reg2, 8);
591 reg0 |= reg2;
610 v8u16 reg0, reg1, reg2; local
774 v8u16 reg0, reg1, reg2, reg3, reg4, reg5; local
826 v8u16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8, reg9; local
1085 v16u8 src0, src1, src2, src3, reg0, reg1, reg2, reg3, dst0, dst1; local
1159 v4u32 reg0, reg1, reg2, reg3; local
1237 v4u32 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; local
1305 v8i16 reg0, reg1, reg2; local
1373 v4u32 reg0, reg1, reg2, reg3, rgba_scale; local
1433 v8u16 reg0, reg1, reg2; local
1506 v16u8 reg0, reg1, reg2, reg3, reg4, reg5, reg6; local
1553 v8u16 reg0, reg1, reg2, reg3, reg4, reg5; local
1648 v8u16 reg0, reg1, reg2, reg3, reg4, reg5; local
1705 v8u16 reg0, reg1, reg2, reg3, reg4, reg5; local
1767 v16u8 src0, src1, src2, reg0, reg1, reg2, reg3, dst0; local
1808 v16u8 src0, src1, src2, reg0, reg1, reg2, reg3, dst0; local
1856 v8u16 src0, src1, src2, src3, reg0, reg1, reg2, reg3; local
1937 v8u16 src0, src1, src2, src3, reg0, reg1, reg2, reg3; local
2020 v8i16 reg0, reg1, reg2, reg3; local
2125 v8i16 reg0, reg1, reg2, reg3; local
2666 v4i32 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8, reg9; local
2729 v4i32 reg0, reg1, reg2, reg3; local
    [all...]
rotate_msa.cc 85 v16u8 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; local
99 ILVRL_H(vec0, vec2, vec1, vec3, reg0, reg1, reg2, reg3);
111 ILVRL_W(reg2, reg6, reg3, reg7, res4, res5, res6, res7);
121 ILVRL_H(vec0, vec2, vec1, vec3, reg0, reg1, reg2, reg3);
142 res8 = (v16u8)__msa_ilvr_w((v4i32)reg6, (v4i32)reg2);
143 res9 = (v16u8)__msa_ilvl_w((v4i32)reg6, (v4i32)reg2);
166 v16u8 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; local
180 ILVRL_H(vec0, vec2, vec1, vec3, reg0, reg1, reg2, reg3);
192 ILVRL_W(reg2, reg6, reg3, reg7, res4, res5, res6, res7);
202 ILVRL_H(vec0, vec2, vec1, vec3, reg0, reg1, reg2, reg3)
    [all...]
scale_msa.cc 70 v8u16 reg0, reg1, reg2, reg3; local
84 reg2 = __msa_hadd_u_h(vec2, vec2);
86 reg0 += reg2;
133 v8u16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; local
159 reg2 = __msa_hadd_u_h(vec2, vec2);
161 reg4 = (v8u16)__msa_pckev_d((v2i64)reg2, (v2i64)reg0);
163 reg6 = (v8u16)__msa_pckod_d((v2i64)reg2, (v2i64)reg0);
296 v4u32 reg0, reg1, reg2, reg3; local
333 reg2 = __msa_hadd_u_w(vec2, vec2);
337 reg2 = (v4u32)__msa_srari_w((v4i32)reg2, 4)
    [all...]
  /device/linaro/bootloader/arm-trusted-firmware/plat/hikey/drivers/
hisi_dvfs.c 216 unsigned int reg2 = 0; local
352 reg2 = read_reg_mask(PMCTRL_ACPUVOLTTIMEOUT, 0x1,
358 } while((reg0 != reg1) || (0x1 != reg2));
375 reg2 = read_reg_mask(PMCTRL_ACPUPLLCTRL, 0x1,
383 (0x1 != reg2));
426 unsigned int reg2 = 0; local
636 reg2 = read_reg_mask(PMCTRL_ACPUVOLTTIMEOUT, 0x1,
642 } while((reg0 != reg1) || (0x1 != reg2));
  /art/compiler/utils/
assembler_test.h 144 template <typename Reg1, typename Reg2, typename ImmType>
145 std::string RepeatTemplatedRegistersImmBits(void (Ass::*f)(Reg1, Reg2, ImmType),
148 const std::vector<Reg2*> reg2_registers,
150 std::string (AssemblerTest::*GetName2)(const Reg2&),
158 for (auto reg2 : reg2_registers) {
161 (assembler_.get()->*f)(*reg1, *reg2, new_imm * multiplier + bias);
170 std::string reg2_string = (this->*GetName2)(*reg2);
196 template <typename Reg1, typename Reg2, typename Reg3, typename ImmType>
197 std::string RepeatTemplatedRegistersImmBits(void (Ass::*f)(Reg1, Reg2, Reg3, ImmType),
200 const std::vector<Reg2*> reg2_registers
    [all...]
  /toolchain/binutils/binutils-2.25/gas/
dw2gencfi.h 78 unsigned reg2; member in struct:cfi_insn_data::__anon115825::__anon115827
  /toolchain/binutils/binutils-2.25/include/opcode/
msp430-decode.h 81 MSP430_Register reg2 : 8; member in struct:__anon116282
rl78.h 78 RL78_Operand_Indirect, /* [reg + reg2 + addend] */
80 RL78_Operand_BitIndirect, /* [reg+reg2+addend].bit */
130 RL78_Register reg2 : 8; member in struct:__anon116292
  /art/compiler/utils/arm/
assembler_arm_test.h 77 template <typename Reg1, typename Reg2>
78 std::string RepeatTemplatedRRIIC(void (Ass::*f)(Reg1, Reg2, Imm, Imm, Cond),
80 const std::vector<Reg2*> reg2_registers,
82 std::string (AssemblerArmTest::*GetName2)(const Reg2&),
137 for (auto reg2 : reg2_registers) {
140 std::string reg2_string = (this->*GetName2)(*reg2);
153 (Base::GetAssembler()->*f)(*reg1, *reg2, i, j, c);
174 template <typename Reg1, typename Reg2>
175 std::string RepeatTemplatedRRiiC(void (Ass::*f)(Reg1, Reg2, Imm, Imm, Cond),
177 const std::vector<Reg2*> reg2_registers
    [all...]
  /external/v8/src/compiler/mips64/
code-generator-mips64.cc 1041 Register reg2 = kScratchReg2; local
1061 Register reg2 = kScratchReg2; local
1081 Register reg2 = kScratchReg2; local
1125 Register reg2 = kScratchReg2; local
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