HomeSort by relevance Sort by last modified time
    Searched refs:reg_src (Results 1 - 6 of 6) sorted by null

  /external/mesa3d/src/gallium/auxiliary/tgsi/
tgsi_lowering.c 85 reg_src(struct tgsi_full_src_register *src, function
143 reg_src(&new_inst.Src[0], src, SWIZ(X, Y, Z, W));
222 reg_src(&new_inst.Src[0], src0, SWIZ(_, Y, _, _));
223 reg_src(&new_inst.Src[1], src1, SWIZ(_, Y, _, _));
234 reg_src(&new_inst.Src[0], src0, SWIZ(_, _, Z, _));
245 reg_src(&new_inst.Src[0], src1, SWIZ(_, _, _, W));
256 reg_src(&new_inst.Src[0], &ctx->imm, SWIZ(Y, _, _, _));
291 reg_src(&new_inst.Src[0], src1, SWIZ(Y, Z, X, _));
292 reg_src(&new_inst.Src[1], src0, SWIZ(Z, X, Y, _));
301 reg_src(&new_inst.Src[0], src0, SWIZ(Y, Z, X, _))
    [all...]
  /external/mesa3d/src/mesa/state_tracker/
st_tgsi_lower_yuv.c 81 reg_src(struct tgsi_full_src_register *src, function
266 reg_src(&inst.Src[0], &ctx->tmp[A].src, SWIZ(X, Y, Z, _));
267 reg_src(&inst.Src[1], &ctx->imm[3], SWIZ(X, Y, Z, _));
274 reg_src(&inst.Src[0], &ctx->tmp[A].src, SWIZ(X, Y, Z, W));
275 reg_src(&inst.Src[1], &ctx->imm[0], SWIZ(X, Y, Z, W));
281 reg_src(&inst.Src[0], &ctx->tmp[A].src, SWIZ(X, Y, Z, W));
282 reg_src(&inst.Src[1], &ctx->imm[1], SWIZ(X, Y, Z, W));
288 reg_src(&inst.Src[0], &ctx->tmp[A].src, SWIZ(X, Y, Z, W));
289 reg_src(&inst.Src[1], &ctx->imm[2], SWIZ(X, Y, Z, W));
295 reg_src(&inst.Src[0], &ctx->imm[3], SWIZ(_, _, _, W))
    [all...]
  /external/google-breakpad/src/third_party/libdisasm/
ia32_reg.c 83 { REG_DWORD_SIZE, reg_gen | reg_src, 0, "esi" },
92 { REG_WORD_SIZE, reg_gen | reg_src, 15, "si" },
libdis.h 125 reg_src = 0x10000, /* array/rep source */ enumerator in enum:x86_reg_type
    [all...]
  /external/mesa3d/src/compiler/nir/
nir_lower_locals_to_regs.c 237 nir_src reg_src = get_deref_reg_src(intrin->variables[0], local
244 mov->dest.dest.reg.reg = reg_src.reg.reg;
245 mov->dest.dest.reg.base_offset = reg_src.reg.base_offset;
246 mov->dest.dest.reg.indirect = reg_src.reg.indirect;
  /external/google-breakpad/src/third_party/libdisasm/swig/
libdisasm_oop.i 76 reg_ret = 0x04000, reg_src = 0x10000,

Completed in 107 milliseconds