| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/mips/ |
| mips32r2.d | 30 0+0050 <[^>]*> 7c073e20 seh \$7,\$7
31 0+0054 <[^>]*> 7c0a4620 seh \$8,\$10
|
| mips32r2.s | 44 seh $7
45 seh $8, $10
|
| mipsr6@mips32r2.d | 31 0+0050 <[^>]*> 7c073e20 seh \$7,\$7
32 0+0054 <[^>]*> 7c0a4620 seh \$8,\$10
|
| micromips@mips32r2.d | 31 [0-9a-f]+ <[^>]*> 00e7 3b3c seh \$7,\$7
32 [0-9a-f]+ <[^>]*> 010a 3b3c seh \$8,\$10
|
| mips16e.d | 36 0+0036 <[^>]*> ecb1 seh \$4
|
| /art/runtime/interpreter/mterp/mips64/ |
| op_const_4.S | 3 seh a0, rINST # sign extend B in rINST
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/pe/ |
| seh-x64-err-1.s | 3 #seh pseudos out of seh_proc block
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/nds32/ |
| to-16bit-v1.s | 24 seh $r0, $r0
25 seh $r7, $r7
|
| alu-1.s | 12 seh $r0, $r1
|
| alu-1.d | 20 0+0028 <[^>]*> seh \$r0, \$r1
|
| /external/llvm/test/MC/Mips/mips32/ |
| invalid-mips32r2.s | 33 seh $v1,$t4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/llvm/test/MC/Mips/mips4/ |
| invalid-mips64r2.s | 31 seh $v1,$t4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/llvm/test/MC/Mips/mips5/ |
| invalid-mips64r2.s | 38 seh $v1,$12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/llvm/test/MC/Mips/mips64/ |
| invalid-mips64r2.s | 30 seh $v1,$12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/clang/test/SemaCXX/ |
| scope-check.cpp | 445 namespace seh { namespace
447 // Jumping into SEH try blocks is not permitted.
481 // Jumping out of SEH try blocks ok in general. (Jumping out of a __finally
630 } // namespace seh
|
| /toolchain/binutils/binutils-2.25/include/opcode/ |
| avr.h | 157 AVR_INSN (seh, "", "1001010001011000", 1, AVR_ISA_1200, 0x9458)
|
| /external/llvm/test/MC/Mips/mips2/ |
| invalid-mips32r2.s | 65 seh $v1,$t4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /art/runtime/interpreter/mterp/mips/ |
| header.S | 159 #define SEH(rd, rt) \
160 seh rd, rt
167 #define SEH(rd, rt) \
|
| /external/llvm/test/MC/Mips/micromips32r6/ |
| valid.s | 109 seh $3, $4 # CHECK: seh $3, $4 # encoding: [0x00,0x64,0x3b,0x3c]
[all...] |
| /external/llvm/test/MC/Mips/mips32r2/ |
| valid.s | 179 seh $v1,$12
|
| /external/llvm/test/MC/Mips/mips32r3/ |
| valid.s | 179 seh $v1,$12
|
| /external/llvm/test/MC/Mips/mips32r5/ |
| valid.s | 180 seh $v1,$12
|
| /external/v8/src/mips/ |
| disasm-mips.cc | [all...] |
| /external/llvm/test/MC/Mips/mips64r2/ |
| valid.s | 252 seh $v1,$12
|
| /external/llvm/test/MC/Mips/mips64r3/ |
| valid.s | 252 seh $v1,$12
|
