| /system/core/libpixelflinger/arch-mips/ |
| t32cb16blend.S | 32 * Uses $t0,$t6,$t7,$t8
52 ext $t8,\dreg,\shift+6+5,5 # dst[\shift:15..11]
53 mul $t6,$t8,$t7
55 ext $t8,\src,3,5 # src[7..3]
57 addu $t8,$t6
59 sll $t8,\shift+11
60 or \fb,$t8
62 sll \fb,$t8,11
66 mul $t8,$t0,$t7
69 srl $t8,
[all...] |
| /toolchain/binutils/binutils-2.25/ld/testsuite/ld-mips-elf/ |
| stub-dynsym-1-10000.d | 9 .*: 3c180001 lui t8,0x1
11 .*: 37180000 ori t8,t8,0x0
|
| stub-dynsym-1-2fe80.d | 9 .*: 3c180002 lui t8,0x2
11 .*: 3718fe80 ori t8,t8,0xfe80
|
| stub-dynsym-1-7fff.d | 10 .*: 24187fff li t8,32767
|
| stub-dynsym-1-8000.d | 10 .*: 34188000 li t8,0x8000
|
| stub-dynsym-1-fff0.d | 10 .*: 3418fff0 li t8,0xfff0
|
| /system/core/libpixelflinger/arch-mips64/ |
| t32cb16blend.S | 31 * Uses $a4,$t2,$t3,$t8
46 ext $t8,\dreg,\shift+6+5,5 # dst[\shift:15..11]
47 mul $t2,$t8,$t3
49 ext $t8,\src,3,5 # src[7..3]
51 addu $t8,$t2
53 sll $t8,\shift+11 # dst[\shift:15..11]
54 or \fb,$t8
56 sll \fb,$t8,11
60 mul $t8,$a4,$t3
63 srl $t8,
[all...] |
| /art/runtime/interpreter/mterp/mips/ |
| header.S | 108 #define t8 $$24 /* two more temp registers */ define
332 lsa t8, rix, rFP, 2; \
333 sw rd, 0(t8); \
334 lsa t8, rix, rREFS, 2; \
335 sw zero, 0(t8)
340 addu t8, rFP, AT; \
341 sw rd, 0(t8); \
342 addu t8, rREFS, AT; \
344 sw zero, 0(t8)
349 lsa t8, rix, rFP, 2;
[all...] |
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/dlx/ |
| itype.s | 13 seqi t7,t8,0x7fff
14 snei t7,t8,0x7fff
15 slti t7,t8,0x7fff
20 sequi t7,t8,0x7fff
21 sneui t7,t8,0x7fff
22 sltui t7,t8,0x7fff
|
| /toolchain/binutils/binutils-2.25/gold/testsuite/ |
| tls_test.h | 39 extern bool t8();
|
| two_file_test.h | 46 extern bool t8();
|
| /bionic/libc/arch-mips/string/ |
| strcmp.S | 110 lbu t8, OFFSET(a0); \
112 beq t8, zero, L(bexit89); \
114 bne t8, t9, L(bexit89)
145 lui t8, 0x0101
146 ori t8, 0x0101
150 dsll t1, t8, 32
151 or t8, t1
164 SUBU t0, v0, t8; \
192 SUBU t0, v0, t8; \
198 SUBU t0, v1, t8; \
[all...] |
| strncmp.S | 112 lbu t8, OFFSET(a0); \
114 beq t8, zero, L(bexit89); \
116 bne t8, t9, L(bexit89)
150 lui t8, 0x0101
151 ori t8, 0x0101
155 dsll t0, t8, 32
156 or t8, t0
177 SUBU t0, v0, t8; \
220 SUBU t0, v0, t8; \
271 EXT t8, v0, POS, 8;
[all...] |
| /external/clang/test/CodeGen/ |
| ms_struct-bitfield-1.c | 70 } ATTR t8; variable in typeref:struct:__anon14964
71 static int a8[(sizeof(t8) == 4) -1];
|
| /external/libjpeg-turbo/simd/ |
| jsimd_mips_dspr2.S | 71 addu t8, t7, s0
72 addu t2, t8, s0
75 lbu t8, 0(t8)
81 sb t8, -1(t5)
107 addu t8, t7, s0
108 addu t2, t8, s0
111 lbu t8, 0(t8)
117 sb t8, -1(t5
[all...] |
| /external/valgrind/none/tests/mips32/ |
| mips32_dspr2.c | [all...] |
| mips32_dsp.c | [all...] |
| /development/ndk/platforms/android-21/arch-mips/include/machine/ |
| regdef.h | 83 #define t8 $24 /* two more temp registers */ macro
|
| /development/ndk/platforms/android-9/arch-mips/include/machine/ |
| regdef.h | 83 #define t8 $24 /* two more temp registers */ macro
|
| /external/clang/test/Sema/ |
| attr-naked.c | 38 __attribute__((naked)) void t8(int z) { // expected-note{{attribute is here}} function
|
| /external/llvm/test/MC/Mips/mips2/ |
| invalid-mips3-wrong-error.s | 10 ldl $t8,-4167($t8) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
|
| /prebuilts/ndk/r10/platforms/android-12/arch-mips/usr/include/machine/ |
| regdef.h | 83 #define t8 $24 /* two more temp registers */ macro
|
| /prebuilts/ndk/r10/platforms/android-13/arch-mips/usr/include/machine/ |
| regdef.h | 83 #define t8 $24 /* two more temp registers */ macro
|
| /prebuilts/ndk/r10/platforms/android-14/arch-mips/usr/include/machine/ |
| regdef.h | 83 #define t8 $24 /* two more temp registers */ macro
|
| /prebuilts/ndk/r10/platforms/android-15/arch-mips/usr/include/machine/ |
| regdef.h | 83 #define t8 $24 /* two more temp registers */ macro
|
