HomeSort by relevance Sort by last modified time
    Searched refs:tmpReg (Results 1 - 3 of 3) sorted by null

  /external/swiftshader/third_party/LLVM/lib/Target/CellSPU/
SPURegisterInfo.cpp 299 unsigned tmpReg = findScratchRegister(II, RS, &SPU::R32CRegClass, SPAdj);
300 BuildMI(MBB, II, dl, TII.get(SPU::ILr32), tmpReg )
303 .addReg(tmpReg, RegState::Kill)
  /system/core/libpixelflinger/codeflinger/
MIPS64Assembler.cpp 358 // note: tmpReg parameter defaults to 1, MIPS register AT
359 int ArmToMips64Assembler::dataProcAdrModes(int op, int& source, bool _signed, int tmpReg)
367 mMips->LUI(tmpReg, (amode.value >> 16));
369 mMips->ORI(tmpReg, tmpReg, (amode.value & 0x0000ffff));
371 source = tmpReg;
379 case LSL: mMips->SLL(tmpReg, amode.reg, amode.value); break;
380 case LSR: mMips->SRL(tmpReg, amode.reg, amode.value); break;
381 case ASR: mMips->SRA(tmpReg, amode.reg, amode.value); break;
382 case ROR: mMips->ROTR(tmpReg, amode.reg, amode.value); break
    [all...]
MIPSAssembler.cpp 371 // note: tmpReg parameter defaults to 1, MIPS register AT
372 int ArmToMipsAssembler::dataProcAdrModes(int op, int& source, bool _signed, int tmpReg)
380 mMips->LUI(tmpReg, (amode.value >> 16));
382 mMips->ORI(tmpReg, tmpReg, (amode.value & 0x0000ffff));
384 source = tmpReg;
392 case LSL: mMips->SLL(tmpReg, amode.reg, amode.value); break;
393 case LSR: mMips->SRL(tmpReg, amode.reg, amode.value); break;
394 case ASR: mMips->SRA(tmpReg, amode.reg, amode.value); break;
396 mMips->ROTR(tmpReg, amode.reg, amode.value)
    [all...]

Completed in 69 milliseconds