| /external/libhevc/common/arm/ |
| ihevc_intra_pred_luma_vert.s | 221 vbsl d18, d24, d16 @only select row values from q12(predpixel)
222 vbsl d10, d25, d16
237 vbsl d8, d24, d16
238 vbsl d6, d25, d16
262 vbsl d18, d24, d16 @only select row values from q12(predpixel)
263 vbsl d10, d25, d16
275 vbsl d8, d24, d16
276 vbsl d6, d25, d16
292 vbsl d18, d24, d16 @only select row values from q12(predpixel)
293 vbsl d10, d25, d1
[all...] |
| ihevc_intra_pred_luma_dc.s | 243 vbsl d19, d15, d2 @first row with dst[0]
255 vbsl d20, d3, d16 @row 1 (prol)
264 vbsl d21, d3, d16 @row 2 (prol)
272 vbsl d20, d3, d16 @row 3 (prol)
280 vbsl d21, d3, d16 @row 4 (prol)
288 vbsl d20, d3, d16 @row 5 (prol)
297 vbsl d21, d3, d16 @row 6 (prol)
306 vbsl d20, d3, d16 @row 7 (prol)
334 vbsl d20, d3, d16 @row 9 (prol)
475 vbsl d19, d15, d2 @first row with dst[0
[all...] |
| ihevc_deblk_luma_horz.s | 504 vbsl d18,d24,d14
511 vbsl d19,d25,d12
533 vbsl d18,d27,d14
537 vbsl d19,d26,d13
|
| ihevc_deblk_luma_vert.s | 517 vbsl d3,d30,d16
527 vbsl d16,d2,d22
573 vbsl d5,d30,d3
584 vbsl d0,d4,d23
|
| /external/llvm/test/MC/ARM/ |
| neont2-bitwise-encoding.s | 51 vbsl d18, d17, d16
52 vbsl q8, q10, q9
54 @ CHECK: vbsl d18, d17, d16 @ encoding: [0x51,0xff,0xb0,0x21]
55 @ CHECK: vbsl q8, q10, q9 @ encoding: [0x54,0xff,0xf2,0x01]
|
| neon-bitwise-encoding.s | 102 vbsl d18, d17, d16
103 vbsl q8, q10, q9
105 @ CHECK: vbsl d18, d17, d16 @ encoding: [0xb0,0x21,0x51,0xf3]
106 @ CHECK: vbsl q8, q10, q9 @ encoding: [0xf2,0x01,0x54,0xf3]
|
| /external/swiftshader/third_party/LLVM/test/MC/ARM/ |
| neont2-bitwise-encoding.s | 51 vbsl d18, d17, d16
52 vbsl q8, q10, q9
54 @ CHECK: vbsl d18, d17, d16 @ encoding: [0x51,0xff,0xb0,0x21]
55 @ CHECK: vbsl q8, q10, q9 @ encoding: [0x54,0xff,0xf2,0x01]
|
| neon-bitwise-encoding.s | 51 vbsl d18, d17, d16
52 vbsl q8, q10, q9
54 @ CHECK: vbsl d18, d17, d16 @ encoding: [0xb0,0x21,0x51,0xf3]
55 @ CHECK: vbsl q8, q10, q9 @ encoding: [0xf2,0x01,0x54,0xf3]
|
| /external/arm-neon-tests/ |
| Android.mk | 26 vcgt vclt vbsl vshl vldX vdup_lane vrshrn_n vqdmull_lane \
|
| ref_vbsl.c | 34 #define TEST_MSG "VBSL/VBSLQ"
37 /* Basic test: y=vbsl(unsigned_vec,x,x), then store the result. */
40 vbsl##Q##_##T2##W(VECT_VAR(vector_first, T3, W, N), \
|
| Makefile | 41 vcgt vclt vbsl vshl vldX vdup_lane vrshrn_n vqdmull_lane \
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/arm/ |
| neon-psyn.s | 71 vbsl q1.8, q2.16, q3.8
|
| neon-psyn.d | 34 0[0-9a-f]+ <[^>]+> f3142156 vbsl q1, q2, q3
|
| neon-cov.s | 160 regs3_ntyp vbsl vbslq
|
| /external/libavc/common/arm/ |
| ih264_resi_trans_quant_a9.s | 218 vbsl.s16 q2, q1, q15 @Restore sign of row 1 and 2
219 vbsl.s16 q3, q4, q0 @Restore sign of row 3 and 4
413 vbsl.s16 q2, q1, q15 @Restore sign of row 1 and 2
414 vbsl.s16 q3, q4, q0 @Restore sign of row 3 and 4
554 vbsl.s16 q3, q13, q11
555 vbsl.s16 q4, q14, q12
669 vbsl.s16 q4, q6, q5 @*sign
|
| /external/libpng/arm/ |
| filter_neon.S | 188 vbsl d28, \rb, \rc
189 vbsl \rx, \ra, d28
|
| /external/pdfium/third_party/libpng16/arm/ |
| filter_neon.S | 188 vbsl d28, \rb, \rc
189 vbsl \rx, \ra, d28
|
| /external/skia/third_party/libpng/arm/ |
| filter_neon.S | 188 vbsl d28, \rb, \rc
189 vbsl \rx, \ra, d28
|
| /external/libvpx/libvpx/vpx_dsp/arm/ |
| loopfilter_neon.c | 294 *op2 = vbsl##r##u8(flat, *op2, p2); \
295 *op1 = vbsl##r##u8(flat, tp1, *op1); \
296 *op0 = vbsl##r##u8(flat, tp0, *op0); \
297 *oq0 = vbsl##r##u8(flat, tq0, *oq0); \
298 *oq1 = vbsl##r##u8(flat, tq1, *oq1); \
299 *oq2 = vbsl##r##u8(flat, *oq2, q2); \
[all...] |
| /external/boringssl/src/crypto/fipsmodule/aes/asm/ |
| bsaes-armv7.pl | 334 vbsl @s[1], @t[1], @t[0]
335 vbsl @s[3], @t[3], @t[2]
338 vbsl @s[0], @s[1], @s[2]
339 vbsl @t[0], @s[2], @s[1]
[all...] |
| /external/boringssl/src/crypto/fipsmodule/sha/asm/ |
| sha512-armv4.pl | 542 vbsl $Ch,$f,$g @ Ch(e,f,g)
556 vbsl $Maj,$c,$b @ Maj(a,b,c)
|
| /external/vixl/src/aarch32/ |
| assembler-aarch32.h | 3928 void vbsl(DataType dt, DRegister rd, DRegister rn, DRegister rm) { function in class:vixl::aarch32::Assembler
3931 void vbsl(DRegister rd, DRegister rn, DRegister rm) { function in class:vixl::aarch32::Assembler
3934 void vbsl(Condition cond, DRegister rd, DRegister rn, DRegister rm) { function in class:vixl::aarch32::Assembler
3940 void vbsl(DataType dt, QRegister rd, QRegister rn, QRegister rm) { function in class:vixl::aarch32::Assembler
3943 void vbsl(QRegister rd, QRegister rn, QRegister rm) { function in class:vixl::aarch32::Assembler
3946 void vbsl(Condition cond, QRegister rd, QRegister rn, QRegister rm) { function in class:vixl::aarch32::Assembler
[all...] |
| disasm-aarch32.h | [all...] |
| /external/valgrind/none/tests/arm/ |
| neon64.stdout.exp | 193 ---- VBSL ----
194 vbsl d0, d1, d2 :: Qd 0x04260426 0x04260426 Qm (i8)0x00000024 Qn (i16)0x00000077
195 vbsl d0, d1, d2 :: Qd 0x05260526 0x01220122 Qm (i8)0x00000024 Qn (i16)0x00000077
196 vbsl d4, d6, d5 :: Qd 0x55575557 0x55575557 Qm (i8)0x000000ff Qn (i16)0x00000057
197 vbsl d4, d6, d5 :: Qd 0x05060506 0x01020102 Qm (i8)0x000000ff Qn (i16)0x00000057
198 vbsl d10, d11, d12 :: Qd 0xfcfcfcfc 0xfcfcfcfc Qm (i8)0x000000fe Qn (i8)0x000000ed
199 vbsl d10, d11, d12 :: Qd 0xadacadac 0xa9a8a9a8 Qm (i8)0x000000fe Qn (i8)0x000000ed
200 vbsl d15, d15, d15 :: Qd 0xffffffff 0xffffffff Qm (i8)0x000000ff Qn (i8)0x000000ff
201 vbsl d15, d15, d15 :: Qd 0xffffffff 0xffffffff Qm (i8)0x000000ff Qn (i8)0x000000ff
202 vbsl d0, d1, d2 :: Qd 0x04260426 0x04260426 Qm (i8)0x00000024 Qn (i16)0x0000007
[all...] |
| /external/v8/src/arm/ |
| assembler-arm.h | [all...] |
