/toolchain/binutils/binutils-2.25/gas/testsuite/gas/arm/ |
neon-ldst-align-bad.s | 0 vld1.8 {d0}, [r0 :128] 2 vld1.8 {q0}, [r0 :256]
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neon-ldst-align-bad.l | 2 [^:]*:1: Error: bad alignment -- `vld1.8 {d0},\[r0:128\]' 3 [^:]*:2: Error: bad alignment -- `vld1.8 {q0},\[r0:256\]'
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macro-vld1.d | 8 \s*0:\s+f420070f\s+vld1.8\s+{d0},\s*\[r0\] 9 \s*4:\s+f420070f\s+vld1.8\s+{d0},\s*\[r0\]
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neon-addressing-bad.l | 2 [^:]*:3: Error: r15 not allowed here -- `vld1.8 {d0},1f' 3 [^:]*:5: Error: r15 not allowed here -- `vld1.8 {D0},R0' 4 [^:]*:6: Error: r15 not allowed here -- `vld1.8 {Q1},R0' 5 [^:]*:7: Error: r15 not allowed here -- `vld1.8 {D0},\[PC\]' 6 [^:]*:8: Error: r15 not allowed here -- `vld1.8 {D0},\[PC,#0\]' 15 [^:]*:17: Error: instruction does not accept this addressing mode -- `vld1.8 {Q0},\[R0,#8\]' 16 [^:]*:18: Error: instruction does not accept this addressing mode -- `vld1.8 {Q0},\[R0,#8\]!' 17 [^:]*:19: Error: instruction does not accept this addressing mode -- `vld1.8 {Q0},\[R0,R1\]' 18 [^:]*:20: Error: instruction does not accept this addressing mode -- `vld1.8 {Q0},\[R0,R1\]!' 19 [^:]*:22: Error: r15 not allowed here -- `vld1.8 {d0},2f [all...] |
macro-vld1.s | 9 sfi_breg r0, vld1.8 {d0}, [\B] 10 sfi_breg r0, vld1.8 { d0 }, [\B]
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neon-ldst-es-bad.s | 2 vld1.64 {d0[1]}, [r0] 3 vld1.64 {d0[]}, [r0]
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neon-ldst-es.s | 12 vld1.16 {d1[],d2[]},[r10] 13 vld1.16 {d1[]},[r10,:16] 20 vld1.8 {d3[7]},[r5]! 25 vld1.8 {d8[2]},[r7] 26 vld1.16 {d8[2]},[r7] 27 vld1.16 {d8[2]},[r7:16] 28 vld1.32 {d8[1]},[r7] 29 vld1.32 {d8[1]},[r7:32] 62 vld1.32 { d1 [ ] } , [ r2 ] , r3 64 vld1.64 {d0}, [r0 [all...] |
/external/libavc/common/arm/ |
ih264_inter_pred_luma_bilinear_a9q.s | 136 vld1.8 {q0}, [r0], r3 @// Load row0 ;src1 137 vld1.8 {q2}, [r1], r4 @// Load row0 ;src2 138 vld1.8 {q1}, [r0], r3 @// Load row1 ;src1 140 vld1.8 {q3}, [r1], r4 @// Load row1 ;src2 142 vld1.8 {q4}, [r0], r3 @// Load row2 ;src1 144 vld1.8 {q5}, [r0], r3 @// Load row3 ;src1 146 vld1.8 {q6}, [r1], r4 @// Load row2 ;src2 148 vld1.8 {q7}, [r1], r4 @// Load row3 ;src2 159 vld1.8 {q0}, [r0], r3 @// Load row4 ;src1 161 vld1.8 {q1}, [r0], r3 @// Load row5 ;src [all...] |
ih264_default_weighted_pred_a9q.s | 124 vld1.32 d0[0], [r0], r3 @load row 1 in source 1 125 vld1.32 d0[1], [r0], r3 @load row 2 in source 1 126 vld1.32 d2[0], [r1], r4 @load row 1 in source 2 127 vld1.32 d2[1], [r1], r4 @load row 2 in source 2 129 vld1.32 d1[0], [r0], r3 @load row 3 in source 1 130 vld1.32 d1[1], [r0], r3 @load row 4 in source 1 132 vld1.32 d3[0], [r1], r4 @load row 3 in source 2 133 vld1.32 d3[1], [r1], r4 @load row 4 in source 2 148 vld1.8 d0, [r0], r3 @load row 1 in source 1 149 vld1.8 d4, [r1], r4 @load row 1 in source [all...] |
/external/libhevc/common/arm/ |
ihevc_intra_pred_luma_mode_18_34.s | 133 vld1.8 {d0},[r8],r6 135 vld1.8 {d1},[r8],r6 137 vld1.8 {d2},[r8],r6 138 vld1.8 {d3},[r8],r6 140 vld1.8 {d4},[r8],r6 141 vld1.8 {d5},[r8],r6 142 vld1.8 {d6},[r8],r6 144 vld1.8 {d7},[r8],r6 164 vld1.8 {d0},[r8],r6 168 vld1.8 {d1},[r8],r [all...] |
ihevc_intra_pred_luma_mode2.s | 122 vld1.8 {d0},[r0],r8 125 vld1.8 {d1},[r10],r8 128 vld1.8 {d2},[r0],r8 129 vld1.8 {d3},[r10],r8 132 vld1.8 {d4},[r0],r8 133 vld1.8 {d5},[r10],r8 134 vld1.8 {d6},[r0],r8 137 vld1.8 {d7},[r10],r8 178 vld1.8 {d0},[r0],r8 181 vld1.8 {d1},[r10],r [all...] |
ihevc_intra_pred_chroma_mode_18_34.s | 134 vld1.8 {d0,d1},[r8],r6 136 vld1.8 {d2,d3},[r8],r6 138 vld1.8 {d4,d5},[r8],r6 140 vld1.8 {d6,d7},[r8],r6 142 vld1.8 {d8,d9},[r8],r6 144 vld1.8 {d10,d11},[r8],r6 146 vld1.8 {d12,d13},[r8],r6 148 vld1.8 {d14,d15},[r8],r6 171 vld1.8 {d0},[r0],r8 174 vld1.8 {d0},[r0],r [all...] |
ihevc_inter_pred_chroma_horz.s | 114 vld1.8 {d0},[r4] @coeff = vld1_s8(pi1_coeff) 161 vld1.u32 {q0},[r12],r11 @vector load pu1_src 163 vld1.u32 {q1},[r12],r11 @vector load pu1_src 165 vld1.u32 {q2},[r12],r11 @vector load pu1_src 167 vld1.u32 {q3},[r12],r9 @vector load pu1_src 171 vld1.u32 {q4},[r4],r11 @vector load pu1_src 173 vld1.u32 {q5},[r4],r11 @vector load pu1_src 175 vld1.u32 {q6},[r4],r11 @vector load pu1_src 177 vld1.u32 {q7},[r4],r9 @vector load pu1_src 218 vld1.u32 {q0},[r12],r11 @vector load pu1_sr [all...] |
ihevc_inter_pred_filters_luma_horz.s | 129 vld1.8 {d0},[r4] @coeff = vld1_s8(pi1_coeff) 191 vld1.u32 {d0},[r12],r11 @vector load pu1_src 192 vld1.u32 {d1},[r12],r11 193 vld1.u32 {d2},[r12],r11 194 vld1.u32 {d3},[r12],r11 215 vld1.u32 {d4},[r12],r11 217 vld1.u32 {d5},[r12],r11 219 vld1.u32 {d6},[r12],r11 221 vld1.u32 {d7},[r12],r11 223 vld1.u32 {d12},[r4],r11 @vector load pu1_src + src_str [all...] |
/external/libmpeg2/common/arm/ |
icv_sad_a9.s | 79 vld1.8 d4, [r0], r2 80 vld1.8 d5, [r1], r3 82 vld1.8 d6, [r0], r2 85 vld1.8 d7, [r1], r3 88 vld1.8 d4, [r0], r2 89 vld1.8 d5, [r1], r3 91 vld1.8 d6, [r0], r2 94 vld1.8 d7, [r1], r3
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impeg2_inter_pred.s | 109 vld1.8 {d0, d1}, [r4], r2 @Load and increment src 113 vld1.8 {d0, d1}, [r4], r2 @Load and increment src 115 vld1.8 {d0, d1}, [r4], r2 @Load and increment src 117 vld1.8 {d0, d1}, [r4], r2 @Load and increment src 119 vld1.8 {d0, d1}, [r4], r2 @Load and increment src 121 vld1.8 {d0, d1}, [r4], r2 @Load and increment src 123 vld1.8 {d0, d1}, [r4], r2 @Load and increment src 125 vld1.8 {d0, d1}, [r4], r2 @Load and increment src 127 vld1.8 {d0, d1}, [r4], r2 @Load and increment src 129 vld1.8 {d0, d1}, [r4], r2 @Load and increment sr [all...] |
/external/libvpx/libvpx/vpx_dsp/arm/ |
vpx_convolve_avg_neon_asm.asm | 36 vld1.8 {q0-q1}, [r0]! 37 vld1.8 {q2-q3}, [r0], lr 39 vld1.8 {q8-q9}, [r6@128]! 40 vld1.8 {q10-q11}, [r6@128], r4 52 vld1.8 {q0-q1}, [r0], r1 53 vld1.8 {q2-q3}, [r0], r1 54 vld1.8 {q8-q9}, [r6@128], r3 55 vld1.8 {q10-q11}, [r6@128], r3 71 vld1.8 {q0}, [r0], r1 72 vld1.8 {q1}, [r0], r [all...] |
vpx_convolve8_avg_neon_asm.asm | 61 vld1.s16 {q0}, [r5] ; filter_x 76 vld1.8 {d24}, [r0], r1 77 vld1.8 {d25}, [r0], r1 78 vld1.8 {d26}, [r0], r1 79 vld1.8 {d27}, [r0], r8 101 vld1.32 {d28[]}, [r0], r1 102 vld1.32 {d29[]}, [r0], r1 103 vld1.32 {d31[]}, [r0], r1 104 vld1.32 {d30[]}, [r0], r8 123 vld1.u32 {d6[0]}, [r2], r [all...] |
/bionic/libc/arch-arm/denver/bionic/ |
memcpy_base.S | 76 vld1.8 {d0}, [r1]! 81 vld1.8 {q0}, [r1]! 85 vld1.8 {q0, q1}, [r1]! 112 vld1.8 {q0, q1}, [r1, :128]! 114 vld1.8 {q0, q1}, [r1, :128]! 119 vld1.8 {q0, q1}, [r1, :128]! 121 vld1.8 {q0, q1}, [r1, :128]! 138 vld1.8 {q0, q1}, [r1]! 140 vld1.8 {q0, q1}, [r1]! 145 vld1.8 {q0, q1}, [r1] [all...] |
memmove.S | 99 vld1.8 {d0}, [r1] 106 vld1.8 {q0}, [r1] 112 vld1.8 {q0, q1}, [r1] 141 vld1.8 {q0, q1}, [r1], r3 143 vld1.8 {q0, q1}, [r1], r3 149 vld1.8 {q0, q1}, [r1], r3 151 vld1.8 {q0, q1}, [r1], r3 175 vld1.8 {q0, q1}, [r1], r3 177 vld1.8 {q0, q1}, [r1], r3 183 vld1.8 {q0, q1}, [r1], r [all...] |
/external/llvm/test/MC/ARM/ |
neon-vld-encoding.s | 3 vld1.8 {d16}, [r0:64] 4 vld1.16 {d16}, [r0] 5 vld1.32 {d16}, [r0] 6 vld1.64 {d16}, [r0] 7 vld1.8 {d16, d17}, [r0:64] 8 vld1.16 {d16, d17}, [r0:128] 9 vld1.32 {d16, d17}, [r0] 10 vld1.64 {d16, d17}, [r0] 11 vld1.8 {d1, d2, d3}, [r3] 12 vld1.16 {d4, d5, d6}, [r3:64 [all...] |
/bionic/libc/arch-arm/cortex-a7/bionic/ |
memcpy_base.S | 101 vld1.8 {d0}, [r1]! 116 vld1.8 {d0 - d3}, [r1]! 122 vld1.8 {d0, d1}, [r1]! 131 vld1.8 {d0 - d3}, [r1]! 135 vld1.8 {d4 - d7}, [r1]! 144 vld1.8 {d0 - d3}, [r1]! 152 vld1.8 {d0, d1}, [r1]! 159 vld1.8 {d0}, [r1]!
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/bionic/libc/arch-arm/kryo/bionic/ |
memcpy.S | 71 vld1.32 {q0, q1}, [r1]! 72 vld1.32 {q2, q3}, [r1]! 73 vld1.32 {q8, q9}, [r1]! 74 vld1.32 {q10, q11}, [r1]! 83 vld1.32 {q0, q1}, [r1]! 84 vld1.32 {q2, q3}, [r1]! 85 vld1.32 {q8, q9}, [r1]! 86 vld1.32 {q10, q11}, [r1]! 102 vld1.32 {q0,q1}, [r1]! 111 vld1.32 {q8}, [r1] [all...] |
/external/boringssl/ios-arm/crypto/fipsmodule/ |
bsaes-armv7.S | 26 @ it can be compiled for either endianness] by courtesy of vld1.8's 1025 vld1.8 {q7}, [r4]! @ load round 0 key 1031 vld1.8 {q15}, [r4]! @ load round 1 key 1064 vld1.8 {q15}, [r4]! @ load next round key 1147 vld1.8 {q15}, [r8] @ load IV 1155 vld1.8 {q0,q1}, [r0]! @ load input 1156 vld1.8 {q2,q3}, [r0]! 1162 vld1.8 {q4,q5}, [r0]! 1164 vld1.8 {q6,q7}, [r0] 1171 vld1.8 {q8,q9}, [r0]! @ reload inpu [all...] |
/external/boringssl/linux-arm/crypto/fipsmodule/ |
bsaes-armv7.S | 27 @ it can be compiled for either endianness] by courtesy of vld1.8's 1020 vld1.8 {q7}, [r4]! @ load round 0 key 1026 vld1.8 {q15}, [r4]! @ load round 1 key 1059 vld1.8 {q15}, [r4]! @ load next round key 1140 vld1.8 {q15}, [r8] @ load IV 1148 vld1.8 {q0,q1}, [r0]! @ load input 1149 vld1.8 {q2,q3}, [r0]! 1155 vld1.8 {q4,q5}, [r0]! 1157 vld1.8 {q6,q7}, [r0] 1164 vld1.8 {q8,q9}, [r0]! @ reload inpu [all...] |