/external/llvm/test/MC/ARM/ |
neon-vswp.s | 3 vswp d1, d2 label 4 vswp q1, q2 label 6 @ CHECK: vswp d1, d2 @ encoding: [0x02,0x10,0xb2,0xf3] 7 @ CHECK: vswp q1, q2 @ encoding: [0x44,0x20,0xb2,0xf3]
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/external/boringssl/ios-arm/crypto/fipsmodule/ |
bsaes-armv7.S | [all...] |
/external/boringssl/linux-arm/crypto/fipsmodule/ |
bsaes-armv7.S | [all...] |
/external/libavc/common/arm/ |
ih264_iquant_itrans_recon_a9.s | 179 vswp d6, d7 @Reverse positions of x2 and x3 186 vswp d12, d13 204 vswp d16, d17 @Reverse positions of x2 and x3 209 vswp d22, d23 353 vswp d6, d7 @Reverse positions of x2 and x3 361 vswp d12, d13 379 vswp d16, d17 @Reverse positions of x2 and x3 385 vswp d22, d23 601 vswp d1, d8 @ Q0/Q1 = Row order x0/x1 602 vswp d3, d10 @ Q2/Q3 = Row order x2/x [all...] |
ih264_ihadamard_scaling_a9.s | 126 vswp d5, d8 @Q2 = x4, Q4 = x6 127 vswp d7, d10 @Q3 = x5, Q5 = x7
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ih264_resi_trans_quant_a9.s | 500 vswp d15, d18 501 vswp d17, d20
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/frameworks/rs/cpu_ref/ |
rsCpuIntrinsics_neon_YuvToRGB.S | 108 vswp d20, d21 187 vswp d20, d21
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rsCpuIntrinsics_neon_Blur.S | 124 vswp d21, d22 148 vswp d21, d22 [all...] |
/external/libhevc/common/arm/ |
ihevc_itrans_recon_8x8.s | 528 vswp d3,d6 531 vswp d5,d8 762 vswp d3,d6 765 vswp d5,d8 852 vswp d11,d14 853 vswp d13,d16
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ihevc_itrans_recon_16x16.s | 1070 vswp d5,d18 1071 vswp d23,d14 1072 vswp d13,d20 1073 vswp d31,d8
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ihevc_itrans_recon_32x32.s | [all...] |
/external/libmpeg2/common/arm/ |
impeg2_idct.s | 796 vswp d3, d6 799 vswp d5, d8 [all...] |
/external/libvpx/libvpx/vpx_dsp/arm/ |
loopfilter_8_neon.asm | 479 ; do the 2 vswp. 480 vswp d0, d4 ; op2 481 vswp d5, d17 ; oq2
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vpx_convolve8_avg_neon_asm.asm | 93 vswp d17, d18
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vpx_convolve8_neon_asm.asm | 93 vswp d17, d18
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loopfilter_16_neon.asm | 219 vswp d23, d25
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/external/libjpeg-turbo/simd/ |
jsimd_arm_neon.S | [all...] |
/external/vixl/src/aarch32/ |
assembler-aarch32.h | 5982 void vswp(DataType dt, DRegister rd, DRegister rm) { vswp(al, dt, rd, rm); } function in class:vixl::aarch32::Assembler 5983 void vswp(DRegister rd, DRegister rm) { function in class:vixl::aarch32::Assembler 5986 void vswp(Condition cond, DRegister rd, DRegister rm) { function in class:vixl::aarch32::Assembler 5991 void vswp(DataType dt, QRegister rd, QRegister rm) { vswp(al, dt, rd, rm); } function in class:vixl::aarch32::Assembler 5992 void vswp(QRegister rd, QRegister rm) { function in class:vixl::aarch32::Assembler 5995 void vswp(Condition cond, QRegister rd, QRegister rm) { function in class:vixl::aarch32::Assembler [all...] |
disasm-aarch32.h | [all...] |
/external/v8/src/arm/ |
assembler-arm.h | [all...] |
macro-assembler-arm.cc | 280 vswp(srcdst0, srcdst1); 292 vswp(srcdst0, srcdst1); [all...] |
/toolchain/binutils/binutils-2.25/gas/testsuite/gas/arm/ |
neon-cov.s | 660 binops vswp vswpq "" 1
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/external/boringssl/src/crypto/poly1305/ |
poly1305_arm_asm.S | 673 # asm 1: vswp <d23=reg128#2%bot,<d01=reg128#12%top 674 # asm 2: vswp <d23=d2,<d01=d23 675 vswp d2,d23 label [all...] |
/external/libavc/encoder/arm/ |
ime_distortion_metrics_a9q.s | 1045 vswp d10, d11 @I rearrange so that the q4 and q5 add properly [all...] |
/external/valgrind/none/tests/arm/ |
neon128.stdout.exp | [all...] |