/external/llvm/test/MC/ARM/ |
neon-table-encoding.s | 3 vtbl.8 d16, {d17}, d16 4 vtbl.8 d16, {d16, d17}, d18 5 vtbl.8 d16, {d16, d17, d18}, d20 6 vtbl.8 d16, {d16, d17, d18, d19}, d20 8 @ CHECK: vtbl.8 d16, {d17}, d16 @ encoding: [0xa0,0x08,0xf1,0xf3] 9 @ CHECK: vtbl.8 d16, {d16, d17}, d18 @ encoding: [0xa2,0x09,0xf0,0xf3] 10 @ CHECK: vtbl.8 d16, {d16, d17, d18}, d20 @ encoding: [0xa4,0x0a,0xf0,0xf3] 11 @ CHECK: vtbl.8 d16, {d16, d17, d18, d19}, d20 @ encoding: [0xa4,0x0b,0xf0,0xf3]
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neont2-table-encoding.s | 5 vtbl.8 d16, {d17}, d16 6 vtbl.8 d16, {d16, d17}, d18 7 vtbl.8 d16, {d16, d17, d18}, d20 8 vtbl.8 d16, {d16, d17, d18, d19}, d20 10 @ CHECK: vtbl.8 d16, {d17}, d16 @ encoding: [0xf1,0xff,0xa0,0x08] 11 @ CHECK: vtbl.8 d16, {d16, d17}, d18 @ encoding: [0xf0,0xff,0xa2,0x09] 12 @ CHECK: vtbl.8 d16, {d16, d17, d18}, d20 @ encoding: [0xf0,0xff,0xa4,0x0a] 13 @ CHECK: vtbl.8 d16, {d16, d17, d18, d19}, d20 @ encoding: [0xf0,0xff,0xa4,0x0b]
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/external/swiftshader/third_party/LLVM/test/MC/ARM/ |
neon-table-encoding.s | 4 @ CHECK: vtbl.8 d16, {d17}, d16 @ encoding: [0xa0,0x08,0xf1,0xf3] 5 vtbl.8 d16, {d17}, d16 6 @ CHECK: vtbl.8 d16, {d16, d17}, d18 @ encoding: [0xa2,0x09,0xf0,0xf3] 7 vtbl.8 d16, {d16, d17}, d18 8 @ CHECK: vtbl.8 d16, {d16, d17, d18}, d20 @ encoding: [0xa4,0x0a,0xf0,0xf3] 9 vtbl.8 d16, {d16, d17, d18}, d20 10 @ CHECK: vtbl.8 d16, {d16, d17, d18, d19}, d20 @ encoding: [0xa4,0x0b,0xf0,0xf3] 11 vtbl.8 d16, {d16, d17, d18, d19}, d20
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neont2-table-encoding.s | 6 @ CHECK: vtbl.8 d16, {d17}, d16 @ encoding: [0xa0,0x08,0xf1,0xff] 7 vtbl.8 d16, {d17}, d16 8 @ CHECK: vtbl.8 d16, {d16, d17}, d18 @ encoding: [0xa2,0x09,0xf0,0xff] 9 vtbl.8 d16, {d16, d17}, d18 10 @ CHECK: vtbl.8 d16, {d16, d17, d18}, d20 @ encoding: [0xa4,0x0a,0xf0,0xff] 11 vtbl.8 d16, {d16, d17, d18}, d20 12 @ CHECK: vtbl.8 d16, {d16, d17, d18, d19}, d20 @ encoding: [0xa4,0x0b,0xf0,0xff] 13 vtbl.8 d16, {d16, d17, d18, d19}, d20
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/external/mesa3d/src/mesa/drivers/dri/i965/ |
gen8_surface_state.c | 82 brw->vtbl.update_renderbuffer_surface = brw_update_renderbuffer_surface; 83 brw->vtbl.emit_null_surface_state = gen8_emit_null_surface_state;
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gen7_wm_surface_state.c | 179 brw->vtbl.update_renderbuffer_surface = brw_update_renderbuffer_surface; 180 brw->vtbl.emit_null_surface_state = gen7_emit_null_surface_state;
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/external/mesa3d/src/mesa/drivers/dri/i915/ |
intel_buffers.h | 45 intel->vtbl.update_draw_buffer(intel);
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intel_batchbuffer.c | 106 if (intel->vtbl.debug_batch != NULL) 107 intel->vtbl.debug_batch(intel); 123 if (unlikely(INTEL_DEBUG & DEBUG_AUB) && intel->vtbl.annotate_aub) 124 intel->vtbl.annotate_aub(intel); 137 intel->vtbl.new_batch(intel); 162 if (intel->vtbl.finish_batch) 163 intel->vtbl.finish_batch(intel);
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/external/mesa3d/src/gallium/auxiliary/pipebuffer/ |
pb_buffer.h | 111 const struct pb_vtbl *vtbl; member in struct:pb_buffer 159 /* Accessor functions for pb->vtbl: 169 return buf->vtbl->map(buf, flags, flush_ctx); 180 buf->vtbl->unmap(buf); 196 assert(buf->vtbl->get_base_buffer); 197 buf->vtbl->get_base_buffer(buf, base_buf, offset); 209 assert(buf->vtbl->validate); 210 return buf->vtbl->validate(buf, vl, flags); 220 assert(buf->vtbl->fence); 221 buf->vtbl->fence(buf, fence) [all...] |
pb_buffer_malloc.c | 58 assert(buf->vtbl == &malloc_buffer_vtbl); 142 buf->base.vtbl = &malloc_buffer_vtbl;
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/frameworks/native/vulkan/include/hardware/ |
hwvulkan.h | 40 * the 'vtbl' field. 51 const void* vtbl; member in union:__anon41538
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/external/mesa3d/src/gallium/auxiliary/util/ |
u_transfer.c | 120 return ur->vtbl->resource_get_handle(screen, resource, handle); 127 ur->vtbl->resource_destroy(screen, resource); 138 return ur->vtbl->transfer_map(context, resource, level, usage, box, 147 ur->vtbl->transfer_flush_region(pipe, transfer, box); 154 ur->vtbl->transfer_unmap(pipe, transfer);
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/external/libhevc/common/arm/ |
ihevc_intra_pred_luma_mode_3_to_9.s | 202 vtbl.8 d12, {d0,d1}, d8 @load from ref_main_idx (row 0) 205 vtbl.8 d13, {d0,d1}, d9 @load from ref_main_idx + 1 (row 0) 209 vtbl.8 d16, {d0,d1}, d4 @load from ref_main_idx (row 1) 213 vtbl.8 d17, {d0,d1}, d5 @load from ref_main_idx + 1 (row 1) 219 vtbl.8 d14, {d0,d1}, d8 @load from ref_main_idx (row 2) 223 vtbl.8 d15, {d0,d1}, d9 @load from ref_main_idx + 1 (row 2) 230 vtbl.8 d10, {d0,d1}, d4 @load from ref_main_idx (row 3) 234 vtbl.8 d11, {d0,d1}, d5 @load from ref_main_idx + 1 (row 3) 241 vtbl.8 d12, {d0,d1}, d8 @load from ref_main_idx (row 4) 245 vtbl.8 d13, {d0,d1}, d9 @load from ref_main_idx + 1 (row 4 [all...] |
ihevc_intra_pred_chroma_mode_3_to_9.s | 197 vtbl.8 d12, {d0,d1,d2,d3}, d8 @load from ref_main_idx (row 0) 200 vtbl.8 d13, {d0,d1,d2,d3}, d9 @load from ref_main_idx + 1 (row 0) 206 vtbl.8 d16, {d0,d1,d2,d3}, d4 @load from ref_main_idx (row 1) 210 vtbl.8 d17, {d0,d1,d2,d3}, d5 @load from ref_main_idx + 1 (row 1) 216 vtbl.8 d14, {d0,d1,d2,d3}, d8 @load from ref_main_idx (row 2) 220 vtbl.8 d15, {d0,d1,d2,d3}, d9 @load from ref_main_idx + 1 (row 2) 227 vtbl.8 d10, {d0,d1,d2,d3}, d4 @load from ref_main_idx (row 3) 231 vtbl.8 d11, {d0,d1,d2,d3}, d5 @load from ref_main_idx + 1 (row 3) 238 vtbl.8 d12, {d0,d1,d2,d3}, d8 @load from ref_main_idx (row 4) 242 vtbl.8 d13, {d0,d1,d2,d3}, d9 @load from ref_main_idx + 1 (row 4 [all...] |
ihevc_intra_pred_filters_luma_mode_11_to_17.s | 312 vtbl.8 d12, {d0,d1}, d8 @load from ref_main_idx (row 0) 315 vtbl.8 d13, {d0,d1}, d9 @load from ref_main_idx + 1 (row 0) 319 vtbl.8 d16, {d0,d1}, d4 @load from ref_main_idx (row 1) 323 vtbl.8 d17, {d0,d1}, d5 @load from ref_main_idx + 1 (row 1) 329 vtbl.8 d14, {d0,d1}, d8 @load from ref_main_idx (row 2) 333 vtbl.8 d15, {d0,d1}, d9 @load from ref_main_idx + 1 (row 2) 340 vtbl.8 d10, {d0,d1}, d4 @load from ref_main_idx (row 3) 344 vtbl.8 d11, {d0,d1}, d5 @load from ref_main_idx + 1 (row 3) 351 vtbl.8 d12, {d0,d1}, d8 @load from ref_main_idx (row 4) 355 vtbl.8 d13, {d0,d1}, d9 @load from ref_main_idx + 1 (row 4 [all...] |
ihevc_intra_pred_filters_chroma_mode_11_to_17.s | 310 vtbl.8 d12, {d0,d1,d2,d3}, d8 @load from ref_main_idx (row 0) 313 vtbl.8 d13, {d0,d1,d2,d3}, d9 @load from ref_main_idx + 1 (row 0) 320 vtbl.8 d16, {d0,d1,d2,d3}, d4 @load from ref_main_idx (row 1) 324 vtbl.8 d17, {d0,d1,d2,d3}, d5 @load from ref_main_idx + 1 (row 1) 330 vtbl.8 d14, {d0,d1,d2,d3}, d8 @load from ref_main_idx (row 2) 334 vtbl.8 d15, {d0,d1,d2,d3}, d9 @load from ref_main_idx + 1 (row 2) 341 vtbl.8 d10, {d0,d1,d2,d3}, d4 @load from ref_main_idx (row 3) 345 vtbl.8 d11, {d0,d1,d2,d3}, d5 @load from ref_main_idx + 1 (row 3) 352 vtbl.8 d12, {d0,d1,d2,d3}, d8 @load from ref_main_idx (row 4) 356 vtbl.8 d13, {d0,d1,d2,d3}, d9 @load from ref_main_idx + 1 (row 4 [all...] |
/external/mesa3d/src/gallium/drivers/i915/ |
i915_resource.h | 100 assert(tex->b.vtbl == &i915_texture_vtbl); 107 assert(tex->b.vtbl == &i915_buffer_vtbl);
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i915_resource_buffer.c | 128 buf->b.vtbl = &i915_buffer_vtbl; 158 buf->b.vtbl = &i915_buffer_vtbl;
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/external/boringssl/src/crypto/fipsmodule/aes/asm/ |
bsaes-armv7.pl | 366 vtbl.8 `&Dlo(@x[0])`, {@t[0]}, `&Dlo($mask)` 367 vtbl.8 `&Dhi(@x[0])`, {@t[0]}, `&Dhi($mask)` 370 vtbl.8 `&Dlo(@x[1])`, {@t[1]}, `&Dlo($mask)` 371 vtbl.8 `&Dhi(@x[1])`, {@t[1]}, `&Dhi($mask)` 374 vtbl.8 `&Dlo(@x[2])`, {@t[2]}, `&Dlo($mask)` 375 vtbl.8 `&Dhi(@x[2])`, {@t[2]}, `&Dhi($mask)` 377 vtbl.8 `&Dlo(@x[3])`, {@t[3]}, `&Dlo($mask)` 378 vtbl.8 `&Dhi(@x[3])`, {@t[3]}, `&Dhi($mask)` 382 vtbl.8 `&Dlo(@x[4])`, {@t[0]}, `&Dlo($mask)` 383 vtbl.8 `&Dhi(@x[4])`, {@t[0]}, `&Dhi($mask) [all...] |
/external/mesa3d/src/mesa/drivers/dri/radeon/ |
radeon_context.c | 126 radeon->vtbl.swtcl_flush = r100_swtcl_flush; 127 radeon->vtbl.pre_emit_state = r100_vtbl_pre_emit_state; 128 radeon->vtbl.fallback = radeonFallback; 129 radeon->vtbl.free_context = r100_vtbl_free_context; 130 radeon->vtbl.emit_query_finish = r100_emit_query_finish; 131 radeon->vtbl.check_blit = r100_check_blit; 132 radeon->vtbl.blit = r100_blit; 133 radeon->vtbl.is_format_renderable = radeonIsFormatRenderable; 134 radeon->vtbl.revalidate_all_buffers = r100ValidateBuffers;
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radeon_common.c | 137 if (rmesa->vtbl.update_scissor) 138 rmesa->vtbl.update_scissor(ctx); 214 radeon->vtbl.fallback(ctx, RADEON_FALLBACK_DRAW_BUFFER, GL_TRUE); 260 radeon->vtbl.fallback(ctx, RADEON_FALLBACK_DRAW_BUFFER, GL_TRUE); 262 radeon->vtbl.fallback(ctx, RADEON_FALLBACK_DRAW_BUFFER, GL_FALSE); 268 radeon->vtbl.fallback(ctx, RADEON_FALLBACK_DEPTH_BUFFER, GL_FALSE); 270 radeon->vtbl.fallback(ctx, RADEON_FALLBACK_DEPTH_BUFFER, GL_TRUE); 273 radeon->vtbl.fallback(ctx, RADEON_FALLBACK_DEPTH_BUFFER, GL_FALSE); 280 radeon->vtbl.fallback(ctx, RADEON_FALLBACK_STENCIL_BUFFER, GL_FALSE); 285 radeon->vtbl.fallback(ctx, RADEON_FALLBACK_STENCIL_BUFFER, GL_TRUE) [all...] |
radeon_pixel_read.c | 109 !radeon->vtbl.check_blit(dst_format, rrb->pitch / rrb->cpp) || !radeon->vtbl.blit) { 158 if (radeon->vtbl.blit(ctx,
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radeon_tex_copy.c | 57 if (!radeon->vtbl.blit) { 101 if (!radeon->vtbl.check_blit(dst_mesaformat, rrb->pitch / rrb->cpp)) { 128 return radeon->vtbl.blit(ctx, rrb->bo, src_offset, src_mesaformat, rrb->pitch/rrb->cpp,
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/external/mesa3d/src/mesa/drivers/dri/r200/ |
r200_context.c | 161 radeon->vtbl.swtcl_flush = r200_swtcl_flush; 162 radeon->vtbl.fallback = r200Fallback; 163 radeon->vtbl.update_scissor = r200_vtbl_update_scissor; 164 radeon->vtbl.emit_query_finish = r200_emit_query_finish; 165 radeon->vtbl.check_blit = r200_check_blit; 166 radeon->vtbl.blit = r200_blit; 167 radeon->vtbl.is_format_renderable = radeonIsFormatRenderable; 168 radeon->vtbl.revalidate_all_buffers = r200ValidateBuffers;
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/toolchain/binutils/binutils-2.25/gas/testsuite/gas/arm/ |
neon-ldst-es.s | 53 vtbl.8 d3,{d4},d5 54 vtbl.8 d3,{q1-q2},d5 55 vtbl.8 d3,{q15},d5
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