| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/aarch64/ |
| inst-directive.d | 8 0: 3619194c tbz w12, #3, 2328 <\.text\+0x2328>
|
| /external/llvm/test/MC/Mips/msa/ |
| set-msa-directive.s | 4 # CHECK: addvi.b $w14, $w12, 14
8 # CHECK: subvi.b $w14, $w12, 14
14 addvi.b $w14, $w12, 14
19 subvi.b $w14, $w12, 14
|
| test_2rf.s | 3 # CHECK: fclass.w $w26, $w12 # encoding: [0x7b,0x20,0x66,0x9e]
10 # CHECK: ffint_s.d $w12, $w15 # encoding: [0x7b,0x3d,0x7b,0x1e]
14 # CHECK: ffql.d $w12, $w13 # encoding: [0x7b,0x35,0x6b,0x1e]
23 # CHECK: frsqrt.w $w12, $w17 # encoding: [0x7b,0x28,0x8b,0x1e]
26 # CHECK: fsqrt.d $w15, $w12 # encoding: [0x7b,0x27,0x63,0xde]
32 # CHECK: ftrunc_s.d $w12, $w27 # encoding: [0x7b,0x23,0xdb,0x1e]
36 fclass.w $w26, $w12
43 ffint_s.d $w12, $w15
47 ffql.d $w12, $w13
56 frsqrt.w $w12, $w1
[all...] |
| test_i5.s | 9 # CHECK: ceqi.w $w12, $w1, -1 # encoding: [0x78,0x5f,0x0b,0x07]
11 # CHECK: clei_s.b $w12, $w16, 1 # encoding: [0x7a,0x01,0x83,0x07]
21 # CHECK: clti_s.w $w12, $w12, 11 # encoding: [0x79,0x4b,0x63,0x07]
41 # CHECK: mini_u.w $w11, $w12, 26 # encoding: [0x7a,0xda,0x62,0xc6]
45 # CHECK: subvi.w $w12, $w10, 11 # encoding: [0x78,0xcb,0x53,0x06]
54 ceqi.w $w12, $w1, -1
56 clei_s.b $w12, $w16, 1
66 clti_s.w $w12, $w12, 1
[all...] |
| set-msa-directive-bad.s | 5 addvi.b $w14, $w12, 14 # CHECK: error: instruction requires a CPU feature not currently enabled
|
| test_3r.s | 26 # CHECK: asub_s.d $w13, $w12, $w12 # encoding: [0x7a,0x6c,0x63,0x51]
37 # CHECK: ave_u.w $w11, $w12, $w11 # encoding: [0x7a,0xcb,0x62,0xd0]
54 # CHECK: binsl.d $w23, $w20, $w12 # encoding: [0x7b,0x6c,0xa5,0xcd]
64 # CHECK: bset.h $w14, $w12, $w6 # encoding: [0x7a,0x26,0x63,0x8d]
65 # CHECK: bset.w $w31, $w9, $w12 # encoding: [0x7a,0x4c,0x4f,0xcd]
82 # CHECK: clt_s.d $w7, $w30, $w12 # encoding: [0x79,0x6c,0xf1,0xcf]
102 # CHECK: dpadd_s.w $w10, $w1, $w12 # encoding: [0x79,0x4c,0x0a,0x93]
107 # CHECK: dpsub_s.h $w4, $w11, $w12 # encoding: [0x7a,0x2c,0x59,0x13]
109 # CHECK: dpsub_s.d $w31, $w12, $w28 # encoding: [0x7a,0x7c,0x67,0xd3
[all...] |
| test_elm.s | 11 sldi.d $w4, $w12[0] # CHECK: sldi.d $w4, $w12[0] # encoding: [0x78,0x38,0x61,0x19]
|
| test_3rf.s | 53 # CHECK: fslt.w $w12, $w5, $w6 # encoding: [0x7b,0x06,0x2b,0x1a]
55 # CHECK: fsne.w $w30, $w1, $w12 # encoding: [0x7a,0xcc,0x0f,0x9c]
58 # CHECK: fsor.d $w12, $w24, $w11 # encoding: [0x7a,0x6b,0xc3,0x1c]
76 # CHECK: maddr_q.w $w29, $w12, $w16 # encoding: [0x7b,0x70,0x67,0x5c]
79 # CHECK: msubr_q.h $w12, $w21, $w11 # encoding: [0x7b,0x8b,0xab,0x1c]
136 fslt.w $w12, $w5, $w6
138 fsne.w $w30, $w1, $w12
141 fsor.d $w12, $w24, $w11
159 maddr_q.w $w29, $w12, $w16
162 msubr_q.h $w12, $w21, $w1
[all...] |
| /system/core/libpixelflinger/arch-arm64/ |
| col32cb16blend.S | 57 and w12, w9, w1, lsr #8 // extract green
60 lsl w12, w12, #6 // prescale green
72 madd w7, w7, w5, w12 // dest green * alpha + src green
|
| t32cb16blend.S | 155 // w12: scratch
169 pixel w3, w4, w12, 0
170 strh w12, [x0], #2
187 pixel w3, w4, w12, 0
188 pixel w3, w5, w12, 1
189 str w12, [x0, #-4]
200 pixel w3, w4, w12, 0
201 pixel w3, w5, w12, 1
202 str w12, [x0, #-4]
|
| /toolchain/binutils/binutils-2.25/ld/testsuite/ld-aarch64/ |
| emit-relocs-279.d | 13 +10018: 3619194c tbz w12, #3, 12340 <target2>
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/mips/ |
| msa.s | 10 slli.b $w12,$w13,0
24 srai.h $w12,$w13,0
38 srli.w $w12,$w13,0
52 bclri.d $w12,$w13,0
66 bneg.b $w12,$w13,$w14
79 binsl.h $w11,$w12,$w13
92 binsr.w $w10,$w11,$w12
106 addvi.b $w12,$w13,0
120 subvi.h $w12,$w13,0
134 maxi_s.w $w12,$w13,-1
[all...] |
| msa-relax.s | 18 bz.w $w12, foo
|
| micromips@msa.d | 13 [0-9a-f]+ <[^>]*> 5870 6b12 slli\.b \$w12,\$w13,0x0
27 [0-9a-f]+ <[^>]*> 58e0 6b12 srai\.h \$w12,\$w13,0x0
41 [0-9a-f]+ <[^>]*> 5940 6b12 srli\.w \$w12,\$w13,0x0
55 [0-9a-f]+ <[^>]*> 5980 6b12 bclri\.d \$w12,\$w13,0x0
69 [0-9a-f]+ <[^>]*> 5a8e 6b1a bneg\.b \$w12,\$w13,\$w14
82 [0-9a-f]+ <[^>]*> 5b2d 62da binsl\.h \$w11,\$w12,\$w13
95 [0-9a-f]+ <[^>]*> 5bcc 5a9a binsr\.w \$w10,\$w11,\$w12
109 [0-9a-f]+ <[^>]*> 5800 6b29 addvi\.b \$w12,\$w13,0
123 [0-9a-f]+ <[^>]*> 58a0 6b29 subvi\.h \$w12,\$w13,0
137 [0-9a-f]+ <[^>]*> 5950 6b29 maxi_s\.w \$w12,\$w13,-1
[all...] |
| /external/libavc/common/armv8/ |
| ih264_intra_pred_luma_16x16_av8.s | 452 sub w12, w8, w9
458 add w12, w12, w8, lsl #1
467 add w12, w12, w8
472 add w12, w12, w5, lsl #2
479 add w12, w12, w8
487 add w12, w12, w5, lsl #
[all...] |
| /external/boringssl/ios-aarch64/crypto/chacha/ |
| chacha-armv8.S | 89 add w8,w8,w12
105 eor w12,w12,w16
109 ror w12,w12,#20
113 add w8,w8,w12
129 eor w12,w12,w16
133 ror w12,w12,#2
[all...] |
| /external/boringssl/linux-aarch64/crypto/chacha/ |
| chacha-armv8.S | 90 add w8,w8,w12
106 eor w12,w12,w16
110 ror w12,w12,#20
114 add w8,w8,w12
130 eor w12,w12,w16
134 ror w12,w12,#2
[all...] |
| /external/libhevc/common/arm64/ |
| ihevc_sao_edge_offset_class0.s | 89 LDRB w12,[x11] //pu1_src_top[wd - 1]
97 STRB w12,[x4] //*pu1_src_top_left = pu1_src_top[wd - 1]
125 LDRB w12,[x7] //pu1_avail[0]
126 mov v3.b[0], w12 //vsetq_lane_s8(pu1_avail[0], au1_mask, 0)
131 mov v3.b[0], w12 //au1_mask = vsetq_lane_s8(-1, au1_mask, 0)
136 LDRB w12,[x7,#1] //pu1_avail[1]
137 mov v3.b[15], w12 //au1_mask = vsetq_lane_s8(pu1_avail[1], au1_mask, 15)
273 LDRB w12,[x7] //pu1_avail[0]
274 mov v3.b[0], w12 //vsetq_lane_s8(pu1_avail[0], au1_mask, 0)
279 mov v3.b[0], w12 //au1_mask = vsetq_lane_s8(-1, au1_mask, 0
[all...] |
| ihevc_sao_edge_offset_class0_chroma.s | 102 LDRH w12,[x20] //pu1_src_top[wd - 1]
106 STRH w12,[x4] //*pu1_src_top_left = pu1_src_top[wd - 1]
143 LDRB w12,[x7] //pu1_avail[0]
144 mov v3.b[0], w12 //vsetq_lane_s8(pu1_avail[0], au1_mask, 0)
145 mov v3.b[1], w12 //vsetq_lane_s8(pu1_avail[0], au1_mask, 1)
150 mov v3.h[0], w12 //au1_mask = vsetq_lane_s8(-1, au1_mask, 0)
155 LDRB w12,[x7,#1] //pu1_avail[1]
156 mov v3.b[14], w12 //au1_mask = vsetq_lane_s8(pu1_avail[1], au1_mask, 14)
157 mov v3.b[15], w12 //au1_mask = vsetq_lane_s8(pu1_avail[1], au1_mask, 15)
330 LDRB w12,[x7] //pu1_avail[0
[all...] |
| /external/openssh/ |
| blocks.c | 56 M(w3 ,w1 ,w12,w4 ) \
64 M(w11,w9 ,w4 ,w12) \
65 M(w12,w10,w5 ,w13) \
67 M(w14,w12,w7 ,w15) \
118 uint64 w12 = load_bigendian(in + 96); local
135 F(w12,0x72be5d74f27b896fULL)
154 F(w12,0xc6e00bf33da88fc2ULL)
173 F(w12,0xd192e819d6ef5218ULL)
192 F(w12,0x90befffa23631e28ULL)
211 F(w12,0x4cc5d4becb3e42b6ULL
[all...] |
| /external/boringssl/ios-aarch64/crypto/fipsmodule/ |
| sha1-armv8.S | 155 add w20,w20,w12 // future e+=X[i]
239 eor w4,w4,w12
314 eor w10,w10,w12
338 eor w12,w12,w14
342 eor w12,w12,w4
346 eor w12,w12,w9
349 ror w12,w12,#3
[all...] |
| sha256-armv8.S | 239 eor w12,w26,w26,ror#14
245 eor w16,w16,w12,ror#11 // Sigma1(e)
246 ror w12,w22,#2
253 eor w17,w12,w17,ror#13 // Sigma0(a)
260 ldp w11,w12,[x1],#2*4
307 rev w12,w12 // 9
316 add w26,w26,w12 // h+=X[i]
486 add w3,w3,w12
526 str w12,[sp,#4
[all...] |
| /external/boringssl/linux-aarch64/crypto/fipsmodule/ |
| sha1-armv8.S | 156 add w20,w20,w12 // future e+=X[i]
240 eor w4,w4,w12
315 eor w10,w10,w12
339 eor w12,w12,w14
343 eor w12,w12,w4
347 eor w12,w12,w9
350 ror w12,w12,#3
[all...] |
| sha256-armv8.S | 240 eor w12,w26,w26,ror#14
246 eor w16,w16,w12,ror#11 // Sigma1(e)
247 ror w12,w22,#2
254 eor w17,w12,w17,ror#13 // Sigma0(a)
261 ldp w11,w12,[x1],#2*4
308 rev w12,w12 // 9
317 add w26,w26,w12 // h+=X[i]
487 add w3,w3,w12
527 str w12,[sp,#4
[all...] |
| /external/llvm/test/MC/Mips/mips32r2/ |
| invalid-msa.s | 15 fexupl.w $w12,$w27 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
17 fexupr.w $w29,$w12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
21 ffint_u.w $w19,$w12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
29 flog2.d $w12,$w16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
31 frcp.d $w12,$w4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
42 ftint_u.w $w12,$w29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
48 nloc.b $w12,$w30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
52 nlzc.b $w12,$w7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
57 or.v $w13,$w23,$w12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
