| /prebuilts/clang/host/linux-x86/clang-3977809/prebuilt_include/llvm/include/llvm/CodeGen/ |
| RegisterScavenging.h | 38 MachineRegisterInfo* MRI;
170 bool isReserved(unsigned Reg) const { return MRI->isReserved(Reg); }
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| VirtRegMap.h | 41 MachineRegisterInfo *MRI;
85 MachineRegisterInfo &getRegInfo() const { return *MRI; }
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| /prebuilts/clang/host/linux-x86/clang-4053586/prebuilt_include/llvm/include/llvm/CodeGen/ |
| RegisterScavenging.h | 38 MachineRegisterInfo* MRI;
170 bool isReserved(unsigned Reg) const { return MRI->isReserved(Reg); }
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| VirtRegMap.h | 41 MachineRegisterInfo *MRI;
85 MachineRegisterInfo &getRegInfo() const { return *MRI; }
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| /external/llvm/include/llvm/CodeGen/GlobalISel/ |
| RegBankSelect.h | 458 /// MRI contains all the register class/bank information that this
460 MachineRegisterInfo *MRI;
602 /// MRI.setRegBank(inst.getOperand(0).getReg(), CurRegBank)
606 /// Tmp = MRI.createNewVirtual(MRI.getSize(ArgReg), CurRegBank)
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| /external/llvm/include/llvm/CodeGen/ |
| LiveIntervalAnalysis.h | 54 MachineRegisterInfo* MRI;
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| LiveRangeEdit.h | 63 MachineRegisterInfo &MRI;
130 : Parent(parent), NewRegs(newRegs), MRI(MF.getRegInfo()), LIS(lis),
134 MRI.setDelegate(this);
137 ~LiveRangeEdit() override { MRI.resetDelegate(this); }
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| MachineTraceMetrics.h | 72 const MachineRegisterInfo *MRI;
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| /external/llvm/include/llvm/Target/ |
| TargetMachine.h | 98 const MCRegisterInfo *MRI;
157 const MCRegisterInfo *getMCRegisterInfo() const { return MRI; }
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| /external/llvm/lib/CodeGen/ |
| ExecutionDepsFix.cpp | 743 const MachineRegisterInfo &MRI = mf.getRegInfo();
745 if (MRI.isPhysRegUsed(Reg)) {
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| RenameIndependentSubregs.cpp | 105 MachineRegisterInfo *MRI;
134 const TargetRegisterClass *RegClass = MRI->getRegClass(Reg);
142 unsigned NewVReg = MRI->createVirtualRegister(RegClass);
176 const TargetRegisterInfo &TRI = *MRI->getTargetRegisterInfo();
179 for (const MachineOperand &MO : MRI->reg_nodbg_operands(Reg)) {
214 const TargetRegisterInfo &TRI = *MRI->getTargetRegisterInfo();
216 for (MachineRegisterInfo::reg_nodbg_iterator I = MRI->reg_nodbg_begin(Reg),
217 E = MRI->reg_nodbg_end(); I != E; ) {
333 for (MachineOperand &MO : MRI->reg_nodbg_operands(Reg)) {
369 MRI = &MF.getRegInfo()
[all...] |
| SplitKit.h | 241 MachineRegisterInfo &MRI;
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| VirtRegMap.cpp | 55 MRI = &mf.getRegInfo();
83 unsigned Hint = MRI->getSimpleHint(VirtReg);
92 std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(VirtReg);
120 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
125 << TRI->getRegClassName(MRI->getRegClass(Reg)) << "\n";
129 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
133 << "] " << TRI->getRegClassName(MRI->getRegClass(Reg)) << "\n";
160 MachineRegisterInfo *MRI;
216 MRI = &MF->getRegInfo();
240 MRI->clearVirtRegs()
[all...] |
| /external/llvm/lib/CodeGen/GlobalISel/ |
| RegisterBankInfo.cpp | 169 RegisterBankInfo::getRegBank(unsigned Reg, const MachineRegisterInfo &MRI,
175 const RegClassOrRegBank &RegClassOrBank = MRI.getRegClassOrRegBank(Reg);
209 const MachineRegisterInfo &MRI = MF.getRegInfo();
235 const RegisterBank *AltRegBank = getRegBank(Reg, MRI, TRI);
272 RegSize = getSizeInBits(Reg, MRI, TRI);
363 const MachineRegisterInfo &MRI,
372 unsigned RegSize = MRI.getSize(Reg);
378 RC = MRI.getRegClass(Reg);
515 MachineRegisterInfo &MRI)
516 : MRI(MRI), MI(MI), InstrMapping(InstrMapping)
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| SelectionDAGBuilder.cpp | [all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64AdvSIMDScalarPass.cpp | 72 MachineRegisterInfo *MRI;
113 const MachineRegisterInfo *MRI) {
117 return MRI->getRegClass(Reg)->hasSuperClassEq(&AArch64::GPR64RegClass);
122 const MachineRegisterInfo *MRI) {
124 return (MRI->getRegClass(Reg)->hasSuperClassEq(&AArch64::FPR64RegClass) &&
126 (MRI->getRegClass(Reg)->hasSuperClassEq(&AArch64::FPR128RegClass) &&
136 const MachineRegisterInfo *MRI,
153 MRI) &&
154 isGPR64(MI->getOperand(1).getReg(), MI->getOperand(1).getSubReg(), MRI))
157 MRI) &
[all...] |
| AArch64ConditionOptimizer.cpp | 90 const MachineRegisterInfo *MRI;
172 } else if (!MRI->use_empty(I->getOperand(0).getReg())) {
326 MRI = &MF.getRegInfo();
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| AArch64RegisterInfo.cpp | 336 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
337 MRI.constrainRegClass(BaseReg, TII->getRegClass(MCID, 0, this, MF));
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| /external/llvm/lib/Target/AArch64/MCTargetDesc/ |
| AArch64AsmBackend.cpp | 376 const MCRegisterInfo &MRI;
386 DarwinAArch64AsmBackend(const Target &T, const MCRegisterInfo &MRI)
387 : AArch64AsmBackend(T, /*IsLittleEndian*/true), MRI(MRI) {}
413 assert(getXRegFromWReg(MRI.getLLVMRegNum(Inst.getRegister(), true)) ==
425 unsigned LRReg = MRI.getLLVMRegNum(LRPush.getRegister(), true);
426 unsigned FPReg = MRI.getLLVMRegNum(FPPush.getRegister(), true);
447 unsigned Reg1 = MRI.getLLVMRegNum(Inst.getRegister(), true);
454 unsigned Reg2 = MRI.getLLVMRegNum(Inst2.getRegister(), true);
575 const MCRegisterInfo &MRI,
[all...] |
| /external/llvm/lib/Target/AMDGPU/ |
| R600OptimizeVectorRegisters.cpp | 51 isImplicitlyDef(MachineRegisterInfo &MRI, unsigned Reg) {
52 for (MachineRegisterInfo::def_instr_iterator It = MRI.def_instr_begin(Reg),
53 E = MRI.def_instr_end(); It != E; ++It) {
56 if (MRI.isReserved(Reg)) {
68 RegSeqInfo(MachineRegisterInfo &MRI, MachineInstr *MI) : Instr(MI) {
73 if (isImplicitlyDef(MRI, MO.getReg()))
88 MachineRegisterInfo *MRI;
192 unsigned DstReg = MRI->createVirtualRegister(&AMDGPU::R600_Reg128RegClass);
219 for (MachineRegisterInfo::use_instr_iterator It = MRI->use_instr_begin(Reg),
220 E = MRI->use_instr_end(); It != E; ++It)
[all...] |
| SIFoldOperands.cpp | 196 MachineRegisterInfo &MRI) {
212 MRI.getRegClass(UseReg) :
240 MRI.getRegClass(DestReg) :
260 RSUse = MRI.use_begin(RegSeqDstReg),
261 RSE = MRI.use_end(); RSUse != RSE; ++RSUse) {
268 CopiesToReplace, TII, TRI, MRI);
301 MachineRegisterInfo &MRI = MF.getRegInfo();
330 !MRI.hasOneUse(MI.getOperand(0).getReg()))
355 Use = MRI.use_begin(MI.getOperand(0).getReg()), E = MRI.use_end()
[all...] |
| SILoadStoreOptimizer.cpp | 62 MachineRegisterInfo *MRI;
86 : MachineFunctionPass(ID), TII(nullptr), TRI(nullptr), MRI(nullptr),
231 unsigned DestReg = MRI->createVirtualRegister(SuperRC);
421 MRI = &MF.getRegInfo();
427 assert(!MRI->isSSA());
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| SIWholeQuadMode.cpp | 96 MachineRegisterInfo *MRI;
263 for (MachineInstr &DefMI : MRI->def_instructions(Use.getReg())) {
397 if (TRI->isSGPRReg(*MRI, Op.getReg())) {
426 SavedWQMReg = MRI->createVirtualRegister(&AMDGPU::SReg_64RegClass);
470 MRI = &MF.getRegInfo();
485 LiveMaskReg = MRI->createVirtualRegister(&AMDGPU::SReg_64RegClass);
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| /external/llvm/lib/Target/ARM/ |
| MLxExpansionPass.cpp | 53 MachineRegisterInfo *MRI;
95 MachineInstr *DefMI = MRI->getVRegDef(Reg);
102 DefMI = MRI->getVRegDef(Reg);
108 DefMI = MRI->getVRegDef(Reg);
120 !MRI->hasOneNonDBGUse(Reg))
124 MachineInstr *UseMI = &*MRI->use_instr_nodbg_begin(Reg);
131 !MRI->hasOneNonDBGUse(Reg))
133 UseMI = &*MRI->use_instr_nodbg_begin(Reg);
149 MachineInstr *DefMI = MRI->getVRegDef(Reg);
160 DefMI = MRI->getVRegDef(SrcReg)
[all...] |
| Thumb1FrameLowering.cpp | 44 const ThumbRegisterInfo &MRI, int NumBytes,
47 MRI, MIFlags);
91 const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo();
228 nullptr, MRI->getDwarfRegNum(Reg, true), MFI->getObjectOffset(FI)));
246 nullptr, MRI->getDwarfRegNum(FramePtr, true), CFAOffset));
253 nullptr, MRI->getDwarfRegNum(FramePtr, true)));
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