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Searched
defs:MRI
(Results
51 - 75
of
390
) sorted by null
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/external/llvm/lib/Target/NVPTX/
NVPTXPeephole.cpp
83
const auto &
MRI
= MF.getRegInfo();
86
GenericAddrDef =
MRI
.getUniqueVRegDef(Op.getReg());
108
const auto &
MRI
= MF.getRegInfo();
110
auto &Prev = *
MRI
.getUniqueVRegDef(Root.getOperand(1).getReg());
120
// Check if
MRI
has only one non dbg use, which is Root
121
if (
MRI
.hasOneNonDBGUse(Prev.getOperand(0).getReg())) {
147
const auto &
MRI
= MF.getRegInfo();
148
if (
MRI
.use_empty(NVPTX::VRFrame)) {
149
if (auto MI =
MRI
.getUniqueVRegDef(NVPTX::VRFrame)) {
/external/llvm/lib/Target/WebAssembly/
WebAssemblyInstrInfo.cpp
57
auto &
MRI
= MBB.getParent()->getRegInfo();
60
?
MRI
.getRegClass(DestReg)
61
:
MRI
.getTargetRegisterInfo()->getMinimalPhysRegClass(DestReg);
/external/llvm/lib/Target/X86/
X86FixupSetCC.cpp
58
MachineRegisterInfo *
MRI
;
121
MRI
= &MF.getRegInfo();
135
for (auto &Use :
MRI
->use_instructions(MI.getOperand(0).getReg()))
163
unsigned ZeroReg =
MRI
->createVirtualRegister(RC);
164
unsigned InsertReg =
MRI
->createVirtualRegister(RC);
177
MRI
->replaceRegWith(ZExt->getOperand(0).getReg(), InsertReg);
/external/swiftshader/third_party/LLVM/lib/CodeGen/
DeadMachineInstructionElim.cpp
33
const MachineRegisterInfo *
MRI
;
74
LivePhysRegs[Reg] : !
MRI
->use_nodbg_empty(Reg)) {
87
MRI
= &MF.getRegInfo();
106
for (MachineRegisterInfo::liveout_iterator LOI =
MRI
->liveout_begin(),
107
LOE =
MRI
->liveout_end(); LOI != LOE; ++LOI) {
142
for (MachineRegisterInfo::use_iterator I =
MRI
->use_begin(Reg),
143
E =
MRI
->use_end(); I!=E; I=nextI) {
/external/swiftshader/third_party/LLVM/lib/MC/MCDisassembler/
Disassembler.h
63
llvm::OwningPtr<const llvm::MCRegisterInfo>
MRI
;
80
const MCRegisterInfo *
mRI
,
87
MRI
.reset(
mRI
);
/prebuilts/clang/host/darwin-x86/clang-3957855/prebuilt_include/llvm/include/llvm/CodeGen/GlobalISel/
MachineIRBuilder.h
44
const MachineRegisterInfo *
MRI
;
/prebuilts/clang/host/darwin-x86/clang-3960126/prebuilt_include/llvm/include/llvm/CodeGen/GlobalISel/
MachineIRBuilder.h
44
const MachineRegisterInfo *
MRI
;
/prebuilts/clang/host/darwin-x86/clang-3977809/prebuilt_include/llvm/include/llvm/CodeGen/GlobalISel/
MachineIRBuilder.h
44
const MachineRegisterInfo *
MRI
;
/prebuilts/clang/host/darwin-x86/clang-4053586/prebuilt_include/llvm/include/llvm/CodeGen/GlobalISel/
MachineIRBuilder.h
44
const MachineRegisterInfo *
MRI
;
/prebuilts/clang/host/linux-x86/clang-3957855/prebuilt_include/llvm/include/llvm/CodeGen/GlobalISel/
MachineIRBuilder.h
44
const MachineRegisterInfo *
MRI
;
/prebuilts/clang/host/linux-x86/clang-3960126/prebuilt_include/llvm/include/llvm/CodeGen/GlobalISel/
MachineIRBuilder.h
44
const MachineRegisterInfo *
MRI
;
/prebuilts/clang/host/linux-x86/clang-3977809/prebuilt_include/llvm/include/llvm/CodeGen/GlobalISel/
MachineIRBuilder.h
44
const MachineRegisterInfo *
MRI
;
/prebuilts/clang/host/linux-x86/clang-4053586/prebuilt_include/llvm/include/llvm/CodeGen/GlobalISel/
MachineIRBuilder.h
44
const MachineRegisterInfo *
MRI
;
/external/llvm/include/llvm/CodeGen/
LiveVariables.h
111
MachineRegisterInfo &
MRI
);
130
MachineRegisterInfo*
MRI
;
285
return getVarInfo(Reg).isLiveIn(MBB, Reg, *
MRI
);
/external/llvm/include/llvm/MC/
MCInstPrinter.h
46
const MCRegisterInfo &
MRI
;
62
const MCRegisterInfo &
mri
)
63
: CommentStream(nullptr), MAI(mai), MII(mii),
MRI
(
mri
), UseMarkup(0),
/external/llvm/lib/CodeGen/
AggressiveAntiDepBreaker.h
114
MachineRegisterInfo &
MRI
;
LiveRangeCalc.h
38
const MachineRegisterInfo *
MRI
;
138
LiveRangeCalc() : MF(nullptr),
MRI
(nullptr), Indexes(nullptr),
OptimizePHIs.cpp
33
MachineRegisterInfo *
MRI
;
69
MRI
= &Fn.getRegInfo();
107
MachineInstr *SrcMI =
MRI
->getVRegDef(SrcReg);
114
SrcMI =
MRI
->getVRegDef(SrcMI->getOperand(1).getReg());
147
for (MachineInstr &UseMI :
MRI
->use_instructions(DstReg)) {
171
if (!
MRI
->constrainRegClass(SingleValReg,
MRI
->getRegClass(OldReg)))
174
MRI
->replaceRegWith(OldReg, SingleValReg);
UnreachableBlockElim.cpp
205
MachineRegisterInfo &
MRI
= F.getRegInfo();
206
MRI
.constrainRegClass(Input,
MRI
.getRegClass(Output));
207
MRI
.replaceRegWith(Output, Input);
/external/llvm/lib/Target/AArch64/
AArch64RedundantCopyElimination.cpp
48
const MachineRegisterInfo *
MRI
;
130
!
MRI
->isReserved(DefReg) &&
173
MRI
= &MF.getRegInfo();
AArch64StorePairSuppress.cpp
32
const MachineRegisterInfo *
MRI
;
124
MRI
= &MF.getRegInfo();
/external/llvm/lib/Target/AMDGPU/MCTargetDesc/
SIMCCodeEmitter.cpp
38
const MCRegisterInfo &
MRI
;
47
SIMCCodeEmitter(const MCInstrInfo &mcii, const MCRegisterInfo &
mri
,
49
: MCII(mcii),
MRI
(
mri
) { }
73
const MCRegisterInfo &
MRI
,
75
return new SIMCCodeEmitter(MCII,
MRI
, Ctx);
214
const MCRegisterClass &RC =
MRI
.getRegClass(RCID);
262
return
MRI
.getEncodingValue(MO.getReg());
284
const MCRegisterClass &RC =
MRI
.getRegClass(RCID);
/external/llvm/lib/Target/AMDGPU/
SILowerI1Copies.cpp
68
MachineRegisterInfo &
MRI
= MF.getRegInfo();
86
const TargetRegisterClass *RC =
MRI
.getRegClass(Reg);
88
MRI
.setRegClass(Reg, &AMDGPU::SReg_64RegClass);
102
const TargetRegisterClass *DstRC =
MRI
.getRegClass(Dst.getReg());
103
const TargetRegisterClass *SrcRC =
MRI
.getRegClass(Src.getReg());
110
MachineInstr *DefInst =
MRI
.getUniqueVRegDef(Src.getReg());
144
MRI
.setRegClass(Reg, &AMDGPU::VGPR_32RegClass);
SIMachineFunctionInfo.cpp
195
MachineRegisterInfo &
MRI
= MF->getRegInfo();
206
unsigned LaneVGPR = TRI->findUnusedRegister(
MRI
, &AMDGPU::VGPR_32RegClass);
/external/llvm/lib/Target/ARM/
Thumb2InstrInfo.cpp
152
MachineRegisterInfo *
MRI
= &MF.getRegInfo();
153
MRI
->constrainRegClass(SrcReg, &ARM::GPRPair_with_gsub_1_in_rGPRRegClass);
193
MachineRegisterInfo *
MRI
= &MF.getRegInfo();
194
MRI
->constrainRegClass(DestReg,
Completed in 412 milliseconds
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