| /external/vixl/test/aarch32/ |
| test-simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32.cc | 154 Register rn; member in struct:vixl::aarch32::__anon38355::Operands
164 uint32_t rn; member in struct:vixl::aarch32::__anon38355::Inputs
1449 Register rn = kTests[i].operands.rn; local
1549 uint32_t rn = results[i]->outputs[j].rn; local
[all...] |
| test-simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32.cc | 154 Register rn; member in struct:vixl::aarch32::__anon38356::Operands
164 uint32_t rn; member in struct:vixl::aarch32::__anon38356::Inputs
1459 Register rn = kTests[i].operands.rn; local
1559 uint32_t rn = results[i]->outputs[j].rn; local
[all...] |
| test-simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32.cc | 154 Register rn; member in struct:vixl::aarch32::__anon38357::Operands
164 uint32_t rn; member in struct:vixl::aarch32::__anon38357::Inputs
1459 Register rn = kTests[i].operands.rn; local
1559 uint32_t rn = results[i]->outputs[j].rn; local
[all...] |
| test-simulator-cond-rd-rn-operand-rm-shift-rs-a32.cc | 154 Register rn; member in struct:vixl::aarch32::__anon38358::Operands
164 uint32_t rn; member in struct:vixl::aarch32::__anon38358::Inputs
2154 Register rn = kTests[i].operands.rn; local
2259 uint32_t rn = results[i]->outputs[j].rn; local
[all...] |
| test-simulator-cond-rd-rn-operand-rm-t32.cc | 168 Register rn; member in struct:vixl::aarch32::__anon38359::Operands
176 uint32_t rn; member in struct:vixl::aarch32::__anon38359::Inputs
1132 Register rn = kTests[i].operands.rn; local
1230 uint32_t rn = results[i]->outputs[j].rn; local
[all...] |
| test-simulator-cond-rd-rn-rm-a32-ge.cc | 146 Register rn; member in struct:vixl::aarch32::__anon38360::Operands
156 uint32_t rn; member in struct:vixl::aarch32::__anon38360::Inputs
394 #include "aarch32/traces/simulator-cond-rd-rn-rm-a32-ge-sadd16.h"
395 #include "aarch32/traces/simulator-cond-rd-rn-rm-a32-ge-sadd8.h"
396 #include "aarch32/traces/simulator-cond-rd-rn-rm-a32-ge-sasx.h"
397 #include "aarch32/traces/simulator-cond-rd-rn-rm-a32-ge-ssax.h"
398 #include "aarch32/traces/simulator-cond-rd-rn-rm-a32-ge-ssub16.h"
399 #include "aarch32/traces/simulator-cond-rd-rn-rm-a32-ge-ssub8.h"
400 #include "aarch32/traces/simulator-cond-rd-rn-rm-a32-ge-uadd16.h"
401 #include "aarch32/traces/simulator-cond-rd-rn-rm-a32-ge-uadd8.h
451 Register rn = kTests[i].operands.rn; local
588 uint32_t rn = results[i]->outputs[j].rn; local
[all...] |
| test-simulator-cond-rd-rn-rm-a32-q.cc | 138 Register rn; member in struct:vixl::aarch32::__anon38361::Operands
148 uint32_t rn; member in struct:vixl::aarch32::__anon38361::Inputs
386 #include "aarch32/traces/simulator-cond-rd-rn-rm-a32-q-qadd.h"
387 #include "aarch32/traces/simulator-cond-rd-rn-rm-a32-q-qdadd.h"
388 #include "aarch32/traces/simulator-cond-rd-rn-rm-a32-q-qdsub.h"
389 #include "aarch32/traces/simulator-cond-rd-rn-rm-a32-q-qsub.h"
397 Register rn,
435 Register rn = kTests[i].operands.rn; local
438 scratch_registers.Exclude(rn);
572 uint32_t rn = results[i]->outputs[j].rn; local
[all...] |
| test-simulator-cond-rd-rn-rm-a32-sel.cc | 134 Register rn; member in struct:vixl::aarch32::__anon38362::Operands
144 uint32_t rn; member in struct:vixl::aarch32::__anon38362::Inputs
382 #include "aarch32/traces/simulator-cond-rd-rn-rm-a32-sel-sel.h"
390 Register rn,
428 Register rn = kTests[i].operands.rn; local
431 scratch_registers.Exclude(rn);
477 __ Ldr(rn, MemOperand(input_ptr, offsetof(Inputs, rn)));
480 (masm.*instruction)(cond, rd, rn, rm)
565 uint32_t rn = results[i]->outputs[j].rn; local
[all...] |
| test-simulator-cond-rd-rn-rm-t32-ge.cc | 146 Register rn; member in struct:vixl::aarch32::__anon38364::Operands
156 uint32_t rn; member in struct:vixl::aarch32::__anon38364::Inputs
394 #include "aarch32/traces/simulator-cond-rd-rn-rm-t32-ge-sadd16.h"
395 #include "aarch32/traces/simulator-cond-rd-rn-rm-t32-ge-sadd8.h"
396 #include "aarch32/traces/simulator-cond-rd-rn-rm-t32-ge-sasx.h"
397 #include "aarch32/traces/simulator-cond-rd-rn-rm-t32-ge-ssax.h"
398 #include "aarch32/traces/simulator-cond-rd-rn-rm-t32-ge-ssub16.h"
399 #include "aarch32/traces/simulator-cond-rd-rn-rm-t32-ge-ssub8.h"
400 #include "aarch32/traces/simulator-cond-rd-rn-rm-t32-ge-uadd16.h"
401 #include "aarch32/traces/simulator-cond-rd-rn-rm-t32-ge-uadd8.h
451 Register rn = kTests[i].operands.rn; local
588 uint32_t rn = results[i]->outputs[j].rn; local
[all...] |
| test-simulator-cond-rd-rn-rm-t32-q.cc | 138 Register rn; member in struct:vixl::aarch32::__anon38365::Operands
148 uint32_t rn; member in struct:vixl::aarch32::__anon38365::Inputs
386 #include "aarch32/traces/simulator-cond-rd-rn-rm-t32-q-qadd.h"
387 #include "aarch32/traces/simulator-cond-rd-rn-rm-t32-q-qdadd.h"
388 #include "aarch32/traces/simulator-cond-rd-rn-rm-t32-q-qdsub.h"
389 #include "aarch32/traces/simulator-cond-rd-rn-rm-t32-q-qsub.h"
397 Register rn,
435 Register rn = kTests[i].operands.rn; local
438 scratch_registers.Exclude(rn);
572 uint32_t rn = results[i]->outputs[j].rn; local
[all...] |
| test-simulator-cond-rd-rn-rm-t32-sel.cc | 134 Register rn; member in struct:vixl::aarch32::__anon38366::Operands
144 uint32_t rn; member in struct:vixl::aarch32::__anon38366::Inputs
382 #include "aarch32/traces/simulator-cond-rd-rn-rm-t32-sel-sel.h"
390 Register rn,
428 Register rn = kTests[i].operands.rn; local
431 scratch_registers.Exclude(rn);
477 __ Ldr(rn, MemOperand(input_ptr, offsetof(Inputs, rn)));
480 (masm.*instruction)(cond, rd, rn, rm)
565 uint32_t rn = results[i]->outputs[j].rn; local
[all...] |
| test-simulator-cond-rd-rn-t32.cc | 141 Register rn; member in struct:vixl::aarch32::__anon38368::Operands
148 uint32_t rn; member in struct:vixl::aarch32::__anon38368::Inputs
1362 Register rn = kTests[i].operands.rn; local
1453 uint32_t rn = results[i]->outputs[j].rn; local
[all...] |
| test-simulator-cond-rdlow-rnlow-operand-immediate-t32.cc | 140 Register rn; member in struct:vixl::aarch32::__anon38370::Operands
148 uint32_t rn; member in struct:vixl::aarch32::__anon38370::Inputs
1432 Register rn = kTests[i].operands.rn; local
1525 uint32_t rn = results[i]->outputs[j].rn; local
[all...] |
| test-simulator-cond-rdlow-rnlow-rmlow-t32.cc | 136 Register rn; member in struct:vixl::aarch32::__anon38371::Operands
144 uint32_t rn; member in struct:vixl::aarch32::__anon38371::Inputs
916 Register rn = kTests[i].operands.rn; local
1013 uint32_t rn = results[i]->outputs[j].rn; local
[all...] |
| test-simulator-rd-rn-rm-a32.cc | 139 Register rn; member in struct:vixl::aarch32::__anon38372::Operands
146 uint32_t rn; member in struct:vixl::aarch32::__anon38372::Inputs
703 Register rn = kTests[i].operands.rn; local
777 uint32_t rn = results[i]->outputs[j].rn; local
[all...] |
| test-simulator-rd-rn-rm-t32.cc | 139 Register rn; member in struct:vixl::aarch32::__anon38373::Operands
146 uint32_t rn; member in struct:vixl::aarch32::__anon38373::Inputs
703 Register rn = kTests[i].operands.rn; local
777 uint32_t rn = results[i]->outputs[j].rn; local
[all...] |
| test-simulator-cond-rd-rn-rm-a32.cc | 192 Register rn; member in struct:vixl::aarch32::__anon38363::Operands
202 uint32_t rn; member in struct:vixl::aarch32::__anon38363::Inputs
1539 Register rn = kTests[i].operands.rn; local
1676 uint32_t rn = results[i]->outputs[j].rn; local
[all...] |
| test-simulator-cond-rd-rn-rm-t32.cc | 191 Register rn; member in struct:vixl::aarch32::__anon38367::Operands
201 uint32_t rn; member in struct:vixl::aarch32::__anon38367::Inputs
1537 Register rn = kTests[i].operands.rn; local
1674 uint32_t rn = results[i]->outputs[j].rn; local
[all...] |
| /toolchain/binutils/binutils-2.25/opcodes/ |
| sh-dis.c | 36 int rn,
53 fprintf_fn (stream, "@r%d", rn);
60 fprintf_fn (stream, "@r%d+", rn);
64 fprintf_fn (stream, "@r%d+r8", rn);
68 fprintf_fn (stream, "@r%d+r9", rn);
501 int rn = 0; local
639 rn = nibs[n];
647 rn = (nibs[n] & 0xc) >> 2;
650 rn = (nibs[n] & 0xc) >> 2;
658 rn = nibs[n]
[all...] |
| /external/e2fsprogs/debugfs/ |
| do_journal.c | 540 size_t bn = 0, rn = 0; local
561 err = read_list(optarg, &rlist, &rn);
595 rlist, rn, fp);
|
| /libcore/ojluni/src/main/java/java/util/ |
| ArraysParallelSortHelpers.java | 171 rn = this.rsize, k = this.wbase, g = this.gran; local
176 if (ln >= rn) {
179 rh = rn;
190 if (rn <= g)
193 T split = a[(rh = rn >>> 1) + rb];
203 rb + rh, rn - rh,
205 rn = rh;
211 int lf = lb + ln, rf = rb + rn; // index bounds
285 rn = this.rsize, k = this.wbase, g = this.gran; local
289 if (ln >= rn) {
396 rn = this.rsize, k = this.wbase, g = this.gran; local
507 rn = this.rsize, k = this.wbase, g = this.gran; local
618 rn = this.rsize, k = this.wbase, g = this.gran; local
729 rn = this.rsize, k = this.wbase, g = this.gran; local
840 rn = this.rsize, k = this.wbase, g = this.gran; local
951 rn = this.rsize, k = this.wbase, g = this.gran; local
[all...] |
| /device/linaro/bootloader/edk2/BaseTools/Source/C/VfrCompile/Pccts/antlr/ |
| antlr.c | 1849 RuleRefNode *rn = (RuleRefNode *)((Junction *)zzaArg(zztasp2,2 ).left)->p1; local
[all...] |
| /external/ipsec-tools/src/racoon/ |
| eaytest.c | 990 vchar_t *rn; local
994 rn = eay_set_random((u_int32_t)96);
995 PVDUMP(rn);
996 vfree(rn);
|
| /external/swiftshader/third_party/subzero/src/DartARM32/ |
| assembler_arm.h | 285 explicit Address(Register rn, int32_t offset = 0, Mode am = Offset) {
293 encoding_ |= static_cast<uint32_t>(rn) << kRnShift;
299 Address(Register rn, Register r, Mode am);
301 Address(Register rn, Register rm,
310 encoding_ = o.encoding() | am | (static_cast<uint32_t>(rn) << kRnShift);
314 Address(Register rn, Register rm, Shift shift, Register r, Mode am = Offset);
329 Register rn() const { function in class:dart::Address
450 void and_(Register rd, Register rn, Operand o, Condition cond = AL);
453 void eor(Register rd, Register rn, Operand o, Condition cond = AL);
456 void sub(Register rd, Register rn, Operand o, Condition cond = AL)
[all...] |
| /toolchain/binutils/binutils-2.25/gas/config/ |
| tc-spu.c | 533 struct reg_name *rn;
538 rn = ch_reg_name;
543 rn = sp_reg_name;
548 rn = reg_name;
553 if (rn[i].length > l
554 && 0 == strncasecmp (param, rn[i].name, rn[i].length))
556 l = rn[i].length;
557 regno = rn[i].regno;
531 struct reg_name *rn; local
|
