| /external/pcre/dist2/src/sljit/ |
| sljitNativeMIPS_64.c | 222 FAIL_IF(push_inst(compiler, SELECT_OP(DCLZ, CLZ) | S(src2) | TA(EQUAL_FLAG) | DA(EQUAL_FLAG), EQUAL_FLAG));
224 FAIL_IF(push_inst(compiler, SELECT_OP(DCLZ, CLZ) | S(src2) | T(dst) | D(dst), DR(dst)));
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/mips/ |
| set-arch.d | 206 00000318 <[^>]*> 70831824 dclz v1,a0
362 00000588 <[^>]*> 70831824 dclz v1,a0
|
| /external/llvm/test/MC/Disassembler/Mips/mips64r2/ |
| valid-mips64r2-el.txt | 88 0x24 0x80 0x30 0x73 # CHECK: dclz $16, $25
267 0x24 0xd0 0x3a 0x71 # CHECK: dclz $26, $9
|
| valid-mips64r2.txt | 407 0x71 0x3a 0xd0 0x24 # CHECK: dclz $26, $9
409 0x73 0x30 0x80 0x24 # CHECK: dclz $16, $25
|
| /external/llvm/test/MC/Mips/mips64/ |
| valid.s | 77 dclz $s0,$25 # CHECK: dclz $16, $25 # encoding: [0x73,0x30,0x80,0x24]
|
| /external/llvm/test/MC/Mips/mips64r2/ |
| valid.s | 77 dclz $s0,$25 # CHECK: dclz $16, $25 # encoding: [0x73,0x30,0x80,0x24]
|
| /external/llvm/test/MC/Mips/mips64r3/ |
| valid.s | 77 dclz $s0,$25 # CHECK: dclz $16, $25 # encoding: [0x73,0x30,0x80,0x24]
|
| /external/llvm/test/MC/Mips/mips64r5/ |
| valid.s | 77 dclz $s0,$25 # CHECK: dclz $16, $25 # encoding: [0x73,0x30,0x80,0x24]
|
| /external/v8/src/mips64/ |
| disasm-mips64.cc | [all...] |
| constants-mips64.h | 485 DCLZ = ((4U << 3) + 4),
[all...] |
| assembler-mips64.cc | 2479 void Assembler::dclz(Register rd, Register rs) { function in class:v8::internal::Assembler
[all...] |
| /external/llvm/lib/Target/Mips/ |
| Mips64InstrInfo.td | 296 def DCLZ : StdMMR6Rel, CountLeading0<"dclz", GPR64Opnd>, CLO_FM<0x24>,
[all...] |
| /external/llvm/test/MC/Mips/mips64r6/ |
| valid.s | 112 dclz $s0,$25 # CHECK: dclz $16, $25 # encoding: [0x03,0x20,0x80,0x52]
|
| /external/llvm/test/MC/Disassembler/Mips/mips64r3/ |
| valid-mips64r3-el.txt | 85 0x24 0x80 0x30 0x73 # CHECK: dclz $16, $25
|
| valid-mips64r3.txt | 405 0x71 0x3a 0xd0 0x24 # CHECK: dclz $26, $9
407 0x73 0x30 0x80 0x24 # CHECK: dclz $16, $25
|
| /external/llvm/test/MC/Disassembler/Mips/mips64r5/ |
| valid-mips64r5-el.txt | 85 0x24 0x80 0x30 0x73 # CHECK: dclz $16, $25
|
| valid-mips64r5.txt | 405 0x71 0x3a 0xd0 0x24 # CHECK: dclz $26, $9
407 0x73 0x30 0x80 0x24 # CHECK: dclz $16, $25
|
| /external/llvm/test/MC/Disassembler/Mips/mips64r6/ |
| valid-mips64r6-el.txt | 102 0x52 0x80 0x20 0x03 # CHECK: dclz $16, $25
|
| valid-mips64r6.txt | 48 0x03 0x20 0x80 0x52 # CHECK: dclz $16, $25
|
| /system/core/libpixelflinger/codeflinger/ |
| mips64_disassem.c | 68 /*16 */ "clz", "clo", "dclz", "dclo", "dsllv", "dlsa", "dsrlv", "dsrav",
|
| mips_disassem.c | 95 /* 0x20 */ "clz", "clo", "rsrv", "rsrv", "dclz", "dclo", "rsrv", "rsrv",
|
| /external/llvm/test/MC/Mips/micromips64r6/ |
| valid.s | 299 dclz $1, $2 # CHECK: dclz $1, $2 # encoding: [0x58,0x22,0x5b,0x3c]
|
| /external/llvm/test/MC/Disassembler/Mips/micromips64r6/ |
| valid.txt | 288 0x58 0x22 0x5b 0x3c # CHECK: dclz $1, $2
|
| /external/llvm/test/MC/Disassembler/Mips/mips64/ |
| valid-mips64-el.txt | 82 0x24 0x80 0x30 0x73 # CHECK: dclz $16, $25
|
| /art/compiler/optimizing/ |
| intrinsics_mips64.cc | 283 __ Dclz(out, in);
317 __ Dclz(out.AsRegister<GpuRegister>(), out.AsRegister<GpuRegister>());
[all...] |
