| /external/valgrind/none/tests/mips64/ |
| move_instructions.stdout.exp-BE | 2 dmtc1, mov.d, dmfc1 :: mem: 0x0 out: 0x0
4 dmtc1, mov.d, dmfc1 :: mem: 0x12bd6aa out: 0x12bd6aa
6 dmtc1, mov.d, dmfc1 :: mem: 0x0 out: 0x0
8 dmtc1, mov.d, dmfc1 :: mem: 0x7e876382d2ab13 out: 0x7e876382d2ab13
10 dmtc1, mov.d, dmfc1 :: mem: 0x9823b6e out: 0x9823b6e
12 dmtc1, mov.d, dmfc1 :: mem: 0x976d6e9ac31510f3 out: 0x976d6e9ac31510f3
14 dmtc1, mov.d, dmfc1 :: mem: 0xd4326d9 out: 0xd4326d9
16 dmtc1, mov.d, dmfc1 :: mem: 0xb7746d775ad6a5fb out: 0xb7746d775ad6a5fb
18 dmtc1, mov.d, dmfc1 :: mem: 0x130476dc out: 0x130476dc
20 dmtc1, mov.d, dmfc1 :: mem: 0x42b0c0a28677b502 out: 0x42b0c0a28677b50
[all...] |
| move_instructions.stdout.exp-LE | 2 dmtc1, mov.d, dmfc1 :: mem: 0x0 out: 0x0
4 dmtc1, mov.d, dmfc1 :: mem: 0x12bd6aa out: 0x12bd6aa
6 dmtc1, mov.d, dmfc1 :: mem: 0x0 out: 0x0
8 dmtc1, mov.d, dmfc1 :: mem: 0x7e876382d2ab13 out: 0x7e876382d2ab13
10 dmtc1, mov.d, dmfc1 :: mem: 0x9823b6e out: 0x9823b6e
12 dmtc1, mov.d, dmfc1 :: mem: 0x976d6e9ac31510f3 out: 0x976d6e9ac31510f3
14 dmtc1, mov.d, dmfc1 :: mem: 0xd4326d9 out: 0xd4326d9
16 dmtc1, mov.d, dmfc1 :: mem: 0xb7746d775ad6a5fb out: 0xb7746d775ad6a5fb
18 dmtc1, mov.d, dmfc1 :: mem: 0x130476dc out: 0x130476dc
20 dmtc1, mov.d, dmfc1 :: mem: 0x42b0c0a28677b502 out: 0x42b0c0a28677b50
[all...] |
| test_fcsr.c | 9 "dmtc1 $t0, $f0" "\n\t"
15 "dmtc1 $t0, $f0" "\n\t"
|
| macro_load_store.h | 54 "dmtc1 $zero, $f0" "\n\t" \
72 "dmtc1 $zero, $f0" "\n\t" \
93 "dmtc1 $t2, $f0" "\n\t" \
110 "dmtc1 $zero, $f0" "\n\t" \
127 "dmtc1 $zero, $f0" "\n\t" \
149 "dmtc1 $t3, $f3" "\n\t" \
|
| change_fp_mode.c | 42 "dmtc1 $t0, $f1\n\t" \
94 "dmtc1 $t0, $f1\n\t" \
117 "dmtc1 $t0, $f2\n\t" \
199 TEST_MT("dmtc1 $t0, $f0");
200 TEST_MT("dmtc1 $t0, $f1");
|
| change_fp_mode.stdout.exp | 20 dmtc1 $t0, $f0 :: lo32(f1): 5a5a, lo32(f0): 90abcdef
21 dmtc1 $t0, $f1 :: lo32(f1): 90abcdef, lo32(f0): 5a5a
69 dmtc1 $t0, $f0 :: lo32(f1): 12345678, lo32(f0): 90abcdef
70 dmtc1 $t0, $f1 :: lo32(f1): 12345678, lo32(f0): 90abcdef
118 dmtc1 $t0, $f0 :: lo32(f1): 5a5a, lo32(f0): 90abcdef
119 dmtc1 $t0, $f1 :: lo32(f1): 90abcdef, lo32(f0): 5a5a
|
| macro_fpu.h | 139 "dmtc1 %2, $f0" "\n\t" \
161 "dmtc1 %2, $f0" "\n\t" \
248 "dmtc1 $zero, $f0" "\n\t" \
295 "dmtc1 $zero, $f0" "\n\t" \
|
| move_instructions.c | 78 "dmtc1 $t0, $f2" "\n\t" \
88 printf("dmtc1, mov.d, dmfc1 :: mem: 0x%llx out: 0x%llx\n", \
101 "dmtc1 $zero, $"#FD "\n\t" \
102 "dmtc1 $zero, $"#FS "\n\t" \
125 "dmtc1 $zero, $"#FD "\n\t" \
145 "dmtc1 $zero, $"#FD "\n\t" \
146 "dmtc1 $zero, $"#FS "\n\t" \
164 "dmtc1 $zero, $"#FD "\n\t" \
165 "dmtc1 $zero, $"#FS "\n\t" \
|
| /external/llvm/test/CodeGen/Mips/ |
| mips64fpimm0.ll | 6 ; CHECK: dmtc1 $zero
|
| int-to-float-conversion.ll | 32 ; 64: dmtc1 ${{[0-9]+}}, $f[[R0:[0-9]+]]
42 ; 64: dmtc1 ${{[0-9]+}}, $f[[R0:[0-9]+]]
|
| fcopysign-f32-f64.ll | 48 ; 64: dmtc1 $[[OR]], $f0
52 ; 64R2: dmtc1 $[[INS]], $f0
|
| fcopysign.ll | 28 ; 64: dmtc1 $[[OR]], $f0
32 ; 64R2: dmtc1 $[[INS]], $f0
|
| fpxx.ll | 43 ; floats/doubles are not passed in integer registers for n64, so dmtc1 is not used.
140 ; 4-NOFPXX: dmtc1 $zero, $f0
142 ; 64-NOFPXX: dmtc1 $zero, $f0
178 ; floats/doubles are not passed in integer registers for n64, so dmtc1 is not used.
181 ; floats/doubles are not passed in integer registers for n64, so dmtc1 is not used.
|
| analyzebranch.ll | 18 ; 64-GPR: dmtc1 $zero, $[[Z:f[0-9]]]
|
| fmadd1.ll | 219 ; 64R6-DAG: dmtc1 $zero, $[[T2:f[0-9]+]]
260 ; 64R6-DAG: dmtc1 $zero, $[[T2:f[0-9]+]]
308 ; 64R6-DAG: dmtc1 $zero, $[[T2:f[0-9]+]]
356 ; 64R6-DAG: dmtc1 $zero, $[[T2:f[0-9]+]]
|
| /external/llvm/test/CodeGen/Mips/cconv/ |
| return-hard-fp128.ll | 24 ; N32-DAG: dmtc1 [[R2]], $f0
25 ; N32-DAG: dmtc1 [[R4]], $f2
30 ; N64-DAG: dmtc1 [[R3]], $f0
31 ; N64-DAG: dmtc1 [[R4]], $f2
|
| return-hard-struct-f128.ll | 27 ; N32-DAG: dmtc1 [[R2]], $f0
30 ; N32-DAG: dmtc1 [[R4]], $f1
34 ; N64-DAG: dmtc1 [[R2]], $f0
36 ; N64-DAG: dmtc1 [[R4]], $f1
|
| /external/llvm/test/CodeGen/Mips/llvm-ir/ |
| ret.ll | 15 ; RUN: llc -march=mips64 -mcpu=mips4 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,NOT-R6
16 ; RUN: llc -march=mips64 -mcpu=mips64 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,NOT-R6
17 ; RUN: llc -march=mips64 -mcpu=mips64r2 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,NOT-R6
18 ; RUN: llc -march=mips64 -mcpu=mips64r3 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,NOT-R6
19 ; RUN: llc -march=mips64 -mcpu=mips64r5 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,NOT-R6
26 ; RUN: llc -march=mips64 -mcpu=mips64r6 -asm-show-inst -disable-mips-delay-filler < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,R6C
166 ; DMTC-DAG: dmtc1 $zero, $f0
198 ; DMTC-DAG: dmtc1 $zero, $f0
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/mips/ |
| li-d.d | 30 [0-9a-f]+ <[^>]*> dmtc1 at,\$f0
|
| micromips.s | [all...] |
| mips-gp64-fp64-pic.d | 88 138: 44a10000 dmtc1 at,\$f0
|
| mips-gp64-fp64-pic.s | 114 # 0180 dmtc1 at,$f0
|
| mips-gp64-fp64.d | 64 d4: 44a10000 dmtc1 at,\$f0
|
| mips-gp64-fp64.s | 68 # 00d4 dmtc1 at,$f0
|
| /external/llvm/lib/Target/Mips/ |
| MipsSEInstrInfo.cpp | 161 Opc = Mips::DMTC1;
375 expandCvtFPInt(MBB, MI, Mips::CVT_S_L, Mips::DMTC1, true);
381 expandCvtFPInt(MBB, MI, Mips::CVT_D64_L, Mips::DMTC1, true);
668 // The case where dmtc1 is available doesn't need to be handled here
|
