| /external/llvm/lib/Target/Mips/ |
| MipsInstrFPU.td | 387 def DMTC1 : MTC1_FT<"dmtc1", FGR64Opnd, GPR64Opnd, II_DMTC1,
622 def : MipsPat<(f64 fpimm0), (DMTC1 ZERO_64)>, FGR_64;
623 def : MipsPat<(f64 fpimm0neg), (FNEG_D64 (DMTC1 ZERO_64))>, FGR_64;
|
| MicroMips64r6InstrInfo.td | 35 class DMTC1_MM64R6_ENC : POOL32F_MFTC1_FM_MMR6<"dmtc1", 0b10110000>;
158 class DMTC1_MM64R6_DESC : MTC1_MMR6_DESC_BASE<"dmtc1", FGR64Opnd, GPR64Opnd,
|
| /external/llvm/test/MC/Mips/mips2/ |
| invalid-mips3.s | 23 dmtc1 $s0,$f14 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| invalid-mips4.s | 23 dmtc1 $s0,$f14 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| invalid-mips5.s | 23 dmtc1 $s0,$f14 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/v8/src/mips64/ |
| macro-assembler-mips64.cc | [all...] |
| disasm-mips64.cc | 1101 case DMTC1:
1102 Format(instr, "dmtc1 'rt, 'fs");
[all...] |
| /external/llvm/test/MC/Mips/mips1/ |
| invalid-mips3.s | 27 dmtc1 $s0,$f14 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| invalid-mips4.s | 25 dmtc1 $s0,$f14 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| invalid-mips5.s | 25 dmtc1 $s0,$f14 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/llvm/test/MC/Disassembler/Mips/mips64/ |
| valid-mips64-el.txt | 88 0x00 0x70 0xb0 0x44 # CHECK: dmtc1 $16, $f14
228 0x00 0x28 0xb7 0x44 # CHECK: dmtc1 $23, $f5
|
| valid-mips64.txt | 213 0x44 0xb0 0x70 0x00 # CHECK: dmtc1 $16, $f14
214 0x44 0xb7 0x28 0x00 # CHECK: dmtc1 $23, $f5
|
| /external/llvm/test/MC/Disassembler/Mips/mips64r2/ |
| valid-mips64r2-el.txt | 94 0x00 0x70 0xb0 0x44 # CHECK: dmtc1 $16, $f14
249 0x00 0x28 0xb7 0x44 # CHECK: dmtc1 $23, $f5
|
| valid-mips64r2.txt | 232 0x44 0xb0 0x70 0x00 # CHECK: dmtc1 $16, $f14
233 0x44 0xb7 0x28 0x00 # CHECK: dmtc1 $23, $f5
|
| /art/runtime/arch/mips64/ |
| quick_entrypoints_mips64.S | [all...] |
| /external/llvm/test/MC/Disassembler/Mips/mips3/ |
| valid-mips3-el.txt | 70 0x00 0x70 0xb0 0x44 # CHECK: dmtc1 $16, $f14
|
| valid-mips3.txt | 144 0x44 0xb0 0x70 0x00 # CHECK: dmtc1 $16, $f14
|
| /external/llvm/test/MC/Disassembler/Mips/mips4/ |
| valid-mips4-el.txt | 74 0x00 0x70 0xb0 0x44 # CHECK: dmtc1 $16, $f14
|
| /external/llvm/test/MC/Disassembler/Mips/mips64r3/ |
| valid-mips64r3-el.txt | 91 0x00 0x70 0xb0 0x44 # CHECK: dmtc1 $16, $f14
|
| valid-mips64r3.txt | 230 0x44 0xb0 0x70 0x00 # CHECK: dmtc1 $16, $f14
231 0x44 0xb7 0x28 0x00 # CHECK: dmtc1 $23, $f5
|
| /external/llvm/test/MC/Disassembler/Mips/mips64r5/ |
| valid-mips64r5-el.txt | 91 0x00 0x70 0xb0 0x44 # CHECK: dmtc1 $16, $f14
|
| valid-mips64r5.txt | 229 0x44 0xb0 0x70 0x00 # CHECK: dmtc1 $16, $f14
230 0x44 0xb7 0x28 0x00 # CHECK: dmtc1 $23, $f5
|
| /external/llvm/test/MC/Mips/mips3/ |
| valid.s | 77 dmtc1 $s0,$f14
|
| /external/llvm/test/MC/Mips/micromips64r6/ |
| valid.s | 203 dmtc1 $19, $f20 # CHECK: dmtc1 $19, $f20 # encoding: [0x56,0x74,0x2c,0x3b]
|
| /prebuilts/go/darwin-x86/src/cmd/internal/obj/mips/ |
| asm0.go | [all...] |
