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  /external/llvm/lib/Target/Hexagon/
HexagonInstrInfo.h 144 /// of specified accumulated instruction latencies in the specified MBB to
  /external/llvm/lib/Transforms/Scalar/
MergedLoadStoreMotion.cpp 20 // latencies, triggering if-conversion, and reducing static code size.
  /external/skia/infra/bots/recipe_modules/core/resources/
elf_symbolizer.py 41 internals and OS pipe latencies).
  /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/
ScheduleDAGFast.cpp 104 /// ForceUnitLatencies - The fast scheduler doesn't care about real latencies.
  /external/walt/android/WALT/app/src/main/java/org/chromium/latency/walt/
ScreenResponseFragment.java 353 "Median screen response latencies (N=%d):\n" +
  /external/webrtc/webrtc/modules/audio_device/ios/
audio_device_unittest_ios.cc 278 // detection and add the calculated delay to list of latencies.
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  /external/llvm/lib/CodeGen/
EarlyIfConversion.cpp 113 // Latencies from Cond+Branch, TReg, and FReg to DstReg.
MachineTraceMetrics.cpp 598 // and instruction latencies. These cycle numbers assume that the CPU can issue
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  /external/llvm/lib/CodeGen/SelectionDAG/
ScheduleDAGFast.cpp 110 /// forceUnitLatencies - The fast scheduler doesn't care about real latencies.
  /external/llvm/lib/Target/ARM/
ARM.td 174 // extra cycle. Take that into account when computing operand latencies.
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ARMBaseInstrInfo.cpp     [all...]
  /external/swiftshader/third_party/LLVM/include/llvm/Target/
TargetInstrInfo.h 346 /// instruction latencies in the specified MBB to enable if-conversion.
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  /external/swiftshader/third_party/LLVM/lib/CodeGen/
ScheduleDAGInstrs.cpp 206 // Check to see if the scheduler cares about latencies.
  /external/webrtc/webrtc/modules/audio_device/android/
audio_device_unittest.cc 285 // detection and add the calculated delay to list of latencies.
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  /external/webrtc/webrtc/sound/
pulseaudiosoundsystem.cc 51 // allowing lower latencies.
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  /system/bt/bta/dm/
bta_dm_pm.cc 715 * some agrresive headsets who use sniff latencies more than
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  /external/swiftshader/third_party/LLVM/lib/Target/ARM/
ARMBaseInstrInfo.cpp     [all...]
  /device/linaro/bootloader/arm-trusted-firmware/docs/
change-log.md 62 `USE_COHERENT_MEM=0`. Enabling this option increases the latencies
  /external/boringssl/src/crypto/fipsmodule/aes/asm/
aesv8-armx.pl 24 # instruction latencies and issue rates. On Cortex-A53, an in-order
  /external/llvm/lib/Target/PowerPC/
PPCInstrInfo.cpp 197 // because they have high latencies (compared to other operations, such and
198 // and/or, which are also associative and commutative, but have low latencies).
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  /external/llvm/include/llvm/Target/
Target.td 430 // This instruction is not expected to be queried for scheduling latencies
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TargetInstrInfo.h 644 /// of specified accumulated instruction latencies in the specified MBB to
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  /external/mesa3d/src/mesa/drivers/dri/i965/
brw_schedule_instructions.cpp     [all...]
  /external/netperf/
Release_Notes 95 measured latencies was larger than 31 bits. This was causing
    [all...]
  /external/valgrind/callgrind/docs/
cl-manual.xml     [all...]

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