| /prebuilts/gcc/linux-x86/host/x86_64-linux-glibc2.15-4.8/sysroot/usr/include/i386-linux-gnu/bits/ |
| fenv.h | 88 /* Floating-point environment where none of the exception is masked. */
|
| /prebuilts/gcc/linux-x86/host/x86_64-linux-glibc2.15-4.8/sysroot/usr/include/linux/ |
| can.h | 91 * @can_id: relevant bits of CAN ID which are not masked out.
|
| /prebuilts/gcc/linux-x86/host/x86_64-linux-glibc2.15-4.8/sysroot/usr/include/x86_64-linux-gnu/bits/ |
| fenv.h | 95 /* Floating-point environment where none of the exception is masked. */
|
| /system/core/sdcard/ |
| sdcard.cpp | 286 * permissions are completely masked off. */
294 * the Android directories are masked off to a single user
379 // permissions are completely masked off.
389 // the Android directories are masked off to a single user
|
| /external/ImageMagick/PerlMagick/demo/ |
| compose-specials.pl | 93 # Masked and Blending Demonstartion
96 $clone->Label('Circle Masked\n(three image)');
|
| /external/google-breakpad/src/processor/ |
| contained_range_map_unittest.cc | 72 ASSERT_TRUE (crm.StoreRange(30, 6, 12)); // storable but totally masked
73 ASSERT_TRUE (crm.StoreRange(40, 8, 13)); // will be totally masked
|
| static_contained_range_map_unittest.cc | 189 ASSERT_TRUE (crm_map_.StoreRange(30, 6, 12)); // storable but totally masked
190 ASSERT_TRUE (crm_map_.StoreRange(40, 8, 13)); // will be totally masked
|
| /external/libchrome/crypto/ |
| p224_spake.cc | 174 // Y* is the other party's masked, Diffie-Hellman value.
177 error_ = "failed to parse peer's masked Diffie-Hellman value";
|
| /external/libvncserver/test/ |
| cursortest.c | 257 rfbBool masked=(c->mask[(i/8)+maskStride*j]<<(i&7))&0x80; local
258 c->alphaSource[i+c->width*j]=(masked?(mode==1?value:0xff-value):0);
|
| /external/llvm/test/CodeGen/AMDGPU/ |
| trunc-cmp-constant.ll | 164 %masked = and i8 %load, 255
165 %ext = sext i8 %masked to i32
|
| /external/llvm/test/Transforms/LoopStrengthReduce/AArch64/ |
| lsr-memset.ll | 60 %mask2.masked = or i64 %mask5, %6
61 %mask = or i64 %mask2.masked, %7
|
| /external/llvm/unittests/Support/ |
| EndianTest.cpp | 44 // Test to make sure that signed right shift of 0xf0000000 is masked
73 // This test ensures that signed right shift of 0xffffaa is masked
|
| /external/valgrind/docs/html/ |
| dist.readme-s390.html | 48 -?The?transactional-execution?facility?is?not?supported;?it?is?masked<br>
50 -?The?vector?facility?is?not?supported;?it?is?masked?off?from?HWCAP.<br>
|
| /external/mesa3d/src/gallium/auxiliary/gallivm/ |
| lp_bld_format_aos.c | 226 LLVMValueRef shifted, casted, scaled, masked; local
295 * into masked = {X, Y, Z, W}
326 masked = LLVMBuildAnd(builder, packed, LLVMConstVector(masks, 4), "");
329 masked = LLVMBuildAnd(builder, shifted, LLVMConstVector(masks, 4), "");
334 casted = LLVMBuildSIToFP(builder, masked, LLVMVectorType(LLVMFloatTypeInContext(gallivm->context), 4), "");
336 casted = LLVMBuildUIToFP(builder, masked, LLVMVectorType(LLVMFloatTypeInContext(gallivm->context), 4), "");
|
| lp_bld_swizzle.c | 535 LLVMValueRef masked; local
540 masked = LLVMBuildAnd(builder, a,
543 shifted = LLVMBuildShl(builder, masked,
546 shifted = LLVMBuildLShr(builder, masked,
549 shifted = masked;
|
| /external/llvm/test/CodeGen/X86/ |
| masked_memop.ll | 7 ; To test for the case where masked load/store is not legal, we should add a run with a target
43 %res = call <16 x i32> @llvm.masked.load.v16i32.p0v16i32(<16 x i32>* %addr, i32 4, <16 x i1>%mask, <16 x i32>undef)
79 %res = call <16 x i32> @llvm.masked.load.v16i32.p0v16i32(<16 x i32>* %addr, i32 4, <16 x i1>%mask, <16 x i32>zeroinitializer)
117 call void @llvm.masked.store.v16i32.p0v16i32(<16 x i32>%val, <16 x i32>* %addr, i32 4, <16 x i1>%mask)
158 %res = call <16 x float> @llvm.masked.load.v16f32.p0v16f32(<16 x float>* %addr, i32 4, <16 x i1>%mask, <16 x float> %dst)
214 %res = call <8 x double> @llvm.masked.load.v8f64.p0v8f64(<8 x double>* %addr, i32 4, <8 x i1>%mask, <8 x double>%dst)
243 %res = call <2 x double> @llvm.masked.load.v2f64.p0v2f64(<2 x double>* %addr, i32 4, <2 x i1>%mask, <2 x double>%dst)
272 %res = call <4 x float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>* %addr, i32 4, <4 x i1>%mask, <4 x float>%dst)
309 %res = call <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>* %addr, i32 4, <4 x i1>%mask, <4 x i32>%dst)
342 call void @llvm.masked.store.v4i32.p0v4i32(<4 x i32>%val, <4 x i32>* %addr, i32 4, <4 x i1>%mask
[all...] |
| /external/webrtc/webrtc/base/ |
| ipaddress.cc | 350 in_addr masked; local
351 masked.s_addr = HostToNetwork32(host_order_ip & mask);
352 return IPAddress(masked);
|
| /bionic/libm/amd64/ |
| fenv.c | 34 * with all exceptions masked.
275 * all exceptions are masked).
|
| /device/linaro/bootloader/edk2/OvmfPkg/Include/IndustryStandard/Xen/ |
| xen.h | 233 * triggered can be masked at source at this very precise
293 * becomes pending while the channel is masked then the 'edge' is lost
|
| /external/icu/android_icu4j/src/main/java/android/icu/text/ |
| TransliterationRuleSet.java | 89 * Close this rule set to further additions, check it for masked rules,
91 * @exception IllegalArgumentException if some rules are masked
|
| /external/icu/icu4c/source/i18n/ |
| ucoleitr.cpp | 468 // TODO: The old code masked the order according to strength and then did a binary search.
472 // FIXME: with a masked search, there might be more than one hit,
|
| /external/icu/icu4j/main/classes/translit/src/com/ibm/icu/text/ |
| TransliterationRuleSet.java | 88 * Close this rule set to further additions, check it for masked rules,
90 * @exception IllegalArgumentException if some rules are masked
|
| /external/llvm/test/MC/Mips/ |
| nacl-mask.s | 97 # are not masked.
159 # are not masked.
|
| /external/mesa3d/src/gallium/drivers/etnaviv/ |
| etnaviv_shader.c | 112 * not masked */
117 * POINT_SIZE_ENABLE is masked
|
| /external/mesa3d/src/mesa/tnl/ |
| t_pipeline.c | 132 /* Hardware default: All exceptions masked, extended double precision,
136 /* All exceptions masked, single precision, round to nearest:
|
