| /external/swiftshader/third_party/LLVM/test/CodeGen/Thumb2/ |
| bfi.ll | 58 %b.masked = and i32 %b, -2
59 %and3 = or i32 %b.masked, %and
|
| /external/valgrind/ |
| README.s390 | 25 - The transactional-execution facility is not supported; it is masked
27 - The vector facility is not supported; it is masked off from HWCAP.
|
| /external/swiftshader/src/Shader/ |
| PixelRoutine.cpp | 1574 Int masked = value; local
1592 Int masked = value; local
1651 Short4 masked = value; local
1669 Short4 masked = value; local
1689 bool masked = (((state.targetFormat[index] == FORMAT_A8B8G8R8 || state.targetFormat[index] == FORMAT_SRGB8_A8) && rgbaWriteMask != 0x0000000F) || local
1695 Short4 masked = value; local
1711 Short4 masked = value; local
1792 Short4 masked = value; local
1809 Short4 masked = value; local
1830 Short4 masked = value; local
1847 Short4 masked = value; local
1866 Short4 masked = value; local
1883 Short4 masked = value; local
2390 Float4 masked = value; local
2407 Float4 masked; local
2497 Float4 masked = value; local
2514 Float4 masked = value; local
2533 Float4 masked = value; local
2550 Float4 masked = value; local
[all...] |
| /external/llvm/test/Transforms/LoopVectorize/X86/ |
| masked_load_store.ll | 21 ;AVX: call <8 x i32> @llvm.masked.load.v8i32.p0v8i32
23 ;AVX: call void @llvm.masked.store.v8i32.p0v8i32
28 ;AVX512: call <16 x i32> @llvm.masked.load.v16i32.p0v16i32
30 ;AVX512: call void @llvm.masked.store.v16i32.p0v16i32
96 ;AVX: call <8 x i32> @llvm.masked.load.v8i32.p1v8i32
98 ;AVX: call void @llvm.masked.store.v8i32.p1v8i32
103 ;AVX512: call <16 x i32> @llvm.masked.load.v16i32.p1v16i32
105 ;AVX512: call void @llvm.masked.store.v16i32.p1v16i32
180 ;AVX: call <8 x float> @llvm.masked.load.v8f32.p0v8f32
182 ;AVX: call void @llvm.masked.store.v8f32.p0v8f3
[all...] |
| gather_scatter.ll | 3 ;AVX1-NOT: llvm.masked
20 ;AVX512: llvm.masked.load.v16i32
21 ;AVX512: llvm.masked.gather.v16f32
22 ;AVX512: llvm.masked.store.v16f32
99 ;AVX512: llvm.masked.gather.v16f32
100 ;AVX512: llvm.masked.store.v16f32
174 ;AVX512: llvm.masked.gather.v16f32
177 ;AVX512: llvm.masked.scatter.v16f32
236 declare void @llvm.masked.scatter.v16f32(<16 x float>, <16 x float*>, i32, <16 x i1>)
|
| /development/ndk/platforms/android-21/arch-x86_64/include/machine/ |
| fpu.h | 39 * with all exceptions masked.
|
| /device/linaro/bootloader/edk2/UefiCpuPkg/Include/Register/ |
| LocalApic.h | 150 UINT32 Mask:1; ///< 0: Not masked, 1: Masked.
169 UINT32 Mask:1; ///< 0: Not masked, 1: Masked.
|
| /external/dng_sdk/source/ |
| dng_sdk_limits.h | 58 /// The maximum number of masked area rectangles.
|
| /external/jmdns/src/javax/jmdns/impl/constants/ |
| DNSLabel.java | 76 * @return masked value
|
| /external/libchrome/base/posix/ |
| eintr_wrapper.h | 8 // that should be masked) to go unnoticed, there is a limit after which the
|
| /external/llvm/test/CodeGen/AMDGPU/ |
| trunc.ll | 75 ; SI: s_and_b32 [[MASKED:s[0-9]+]], 1, s[[SLO]]
76 ; SI: v_cmp_eq_i32_e64 s{{\[}}[[VLO:[0-9]+]]:[[VHI:[0-9]+]]], 1, [[MASKED]]
87 ; SI: v_and_b32_e32 [[MASKED:v[0-9]+]], 1, v[[VLO]]
88 ; SI: v_cmp_eq_i32_e32 vcc, 1, [[MASKED]]
|
| /external/llvm/test/Transforms/InstCombine/ |
| icmp-logical.ll | 131 %masked = and i32 %in, 1
132 %tst2 = icmp eq i32 %masked, 0
145 %masked = and i32 %in, 1
146 %tst1 = icmp eq i32 %masked, 0
|
| /prebuilts/ndk/r10/platforms/android-21/arch-x86_64/usr/include/machine/ |
| fpu.h | 39 * with all exceptions masked.
|
| /prebuilts/ndk/r10/platforms/android-23/arch-x86_64/usr/include/machine/ |
| fpu.h | 39 * with all exceptions masked.
|
| /prebuilts/ndk/r11/platforms/android-21/arch-x86_64/usr/include/machine/ |
| fpu.h | 39 * with all exceptions masked.
|
| /prebuilts/ndk/r11/platforms/android-23/arch-x86_64/usr/include/machine/ |
| fpu.h | 39 * with all exceptions masked.
|
| /prebuilts/ndk/r11/platforms/android-24/arch-x86_64/usr/include/machine/ |
| fpu.h | 39 * with all exceptions masked.
|
| /external/llvm/test/Transforms/InstSimplify/ |
| call.ll | 212 %masked.load = call <8 x i32> @llvm.masked.load.v8i32.p0v8i32(<8 x i32>* bitcast (i32* getelementptr ([8 x i32], [8 x i32]* @GV, i64 0, i64 -2) to <8 x i32>*), i32 4, <8 x i1> <i1 false, i1 false, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>, <8 x i32> undef)
213 ret <8 x i32> %masked.load
219 %masked.load = call <8 x i32> @llvm.masked.load.v8i32.p0v8i32(<8 x i32>* %V, i32 4, <8 x i1> undef, <8 x i32> <i32 1, i32 0, i32 1, i32 0, i32 1, i32 0, i32 1, i32 0>)
220 ret <8 x i32> %masked.load
225 declare <8 x i32> @llvm.masked.load.v8i32.p0v8i32(<8 x i32>*, i32, <8 x i1>, <8 x i32>)
|
| /external/llvm/lib/Target/AMDGPU/ |
| R600ExpandSpecialInstrs.cpp | 252 // TO_Y (write masked) = DP4 T1_Y, T2_Y
253 // TO_Z (write masked) = DP4 T1_Z, T2_Z
254 // TO_W (write masked) = DP4 T1_W, T2_W
260 // T0_Y (write masked) = MULLO_INT T1_X, T2_X
261 // T0_Z (write masked) = MULLO_INT T1_X, T2_X
262 // T0_W (write masked) = MULLO_INT T1_X, T2_X
|
| /external/llvm/test/CodeGen/X86/ |
| masked_gather_scatter.ll | 48 %res = call <16 x float> @llvm.masked.gather.v16f32(<16 x float*> %gep.random, i32 4, <16 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>, <16 x float> undef)
52 declare <16 x i32> @llvm.masked.gather.v16i32(<16 x i32*>, i32, <16 x i1>, <16 x i32>)
53 declare <16 x float> @llvm.masked.gather.v16f32(<16 x float*>, i32, <16 x i1>, <16 x float>)
54 declare <8 x i32> @llvm.masked.gather.v8i32(<8 x i32*> , i32, <8 x i1> , <8 x i32> )
97 %res = call <16 x float> @llvm.masked.gather.v16f32(<16 x float*> %gep.random, i32 4, <16 x i1> %imask, <16 x float>undef)
130 %res = call <16 x i32> @llvm.masked.gather.v16i32(<16 x i32*> %gep.random, i32 4, <16 x i1> %imask, <16 x i32>undef)
172 %gt1 = call <16 x i32> @llvm.masked.gather.v16i32(<16 x i32*> %gep.random, i32 4, <16 x i1> %imask, <16 x i32>undef)
173 %gt2 = call <16 x i32> @llvm.masked.gather.v16i32(<16 x i32*> %gep.random, i32 4, <16 x i1> %imask, <16 x i32>%gt1)
224 call void @llvm.masked.scatter.v16i32(<16 x i32>%val, <16 x i32*> %gep.random, i32 4, <16 x i1> %imask)
225 call void @llvm.masked.scatter.v16i32(<16 x i32>%val, <16 x i32*> %gep.random, i32 4, <16 x i1> %imask
[all...] |
| /device/linaro/bootloader/edk2/OvmfPkg/Include/IndustryStandard/Xen/ |
| event_channel.h | 42 * notifications are masked until the bit is cleared again (therefore,
46 * Event notifications can be masked by setting a flag; this is
|
| /external/llvm/test/Transforms/SampleProfile/ |
| inline-act.ll | 36 %switch.masked = trunc i4 %switch.downshift to i1
37 ret i1 %switch.masked
|
| /external/ltp/testcases/kernel/syscalls/rt_sigprocmask/ |
| rt_sigprocmask01.c | 114 /* Make sure that the masked process is indeed
115 * masked. */
|
| /external/ltp/testcases/open_posix_testsuite/conformance/interfaces/sigaction/ |
| 23-1.c | 92 FAILED("Signal was not masked in signal handler");
97 /* Raise the signal again. It should be masked */
|
| 23-10.c | 92 FAILED("Signal was not masked in signal handler");
97 /* Raise the signal again. It should be masked */
|
