| /bionic/libc/ |
| libstdc++.x86_64.map | 9 _Znam; # arm64 x86_64 mips64
10 _ZnamRKSt9nothrow_t; # arm64 x86_64 mips64
11 _Znwm; # arm64 x86_64 mips64
12 _ZnwmRKSt9nothrow_t; # arm64 x86_64 mips64
|
| /system/core/libpixelflinger/tests/arch-mips64/ |
| Android.mk | 1 ifeq ($(TARGET_ARCH),mips64)
|
| /art/compiler/utils/mips64/ |
| assembler_mips64_test.cc | 32 bool operator()(const mips64::GpuRegister& a, const mips64::GpuRegister& b) const {
37 class AssemblerMIPS64Test : public AssemblerTest<mips64::Mips64Assembler,
38 mips64::GpuRegister,
39 mips64::FpuRegister,
41 mips64::VectorRegister> {
43 typedef AssemblerTest<mips64::Mips64Assembler,
44 mips64::GpuRegister,
45 mips64::FpuRegister,
47 mips64::VectorRegister> Base
[all...] |
| /art/runtime/interpreter/mterp/mips64/ |
| op_double_to_int.S | 1 %include "mips64/fcvtHeader.S" { "suffix":"_DOUBLE", "valreg":"f0" }
3 %include "mips64/fcvtFooter.S" { "suffix":"_FLOAT", "valreg":"f0" }
|
| op_double_to_long.S | 1 %include "mips64/fcvtHeader.S" { "suffix":"_DOUBLE", "valreg":"f0" }
3 %include "mips64/fcvtFooter.S" { "suffix":"_DOUBLE", "valreg":"f0" }
|
| op_float_to_int.S | 1 %include "mips64/fcvtHeader.S" { "suffix":"_FLOAT", "valreg":"f0" }
3 %include "mips64/fcvtFooter.S" { "suffix":"_FLOAT", "valreg":"f0" }
|
| op_float_to_long.S | 1 %include "mips64/fcvtHeader.S" { "suffix":"_FLOAT", "valreg":"f0" }
3 %include "mips64/fcvtFooter.S" { "suffix":"_DOUBLE", "valreg":"f0" }
|
| op_neg_double.S | 1 %include "mips64/fcvtHeader.S" { "suffix":"_DOUBLE", "valreg":"f0" }
3 %include "mips64/fcvtFooter.S" { "suffix":"_DOUBLE", "valreg":"f0" }
|
| op_neg_float.S | 1 %include "mips64/fcvtHeader.S" { "suffix":"_FLOAT", "valreg":"f0" }
3 %include "mips64/fcvtFooter.S" { "suffix":"_FLOAT", "valreg":"f0" }
|
| op_long_to_int.S | 2 %include "mips64/op_move.S"
|
| /external/llvm/test/MC/Mips/ |
| mips-coprocessor-encodings.s | 1 # RUN: llvm-mc %s -triple=mips64-unknown-freebsd -show-encoding \
2 # RUN:| FileCheck --check-prefix=MIPS64 %s
4 # MIPS64: dmtc0 $12, $16, 2 # encoding: [0x40,0xac,0x80,0x02]
5 # MIPS64: dmtc0 $12, $16, 0 # encoding: [0x40,0xac,0x80,0x00]
6 # MIPS64: mtc0 $12, $16, 2 # encoding: [0x40,0x8c,0x80,0x02]
7 # MIPS64: mtc0 $12, $16, 0 # encoding: [0x40,0x8c,0x80,0x00]
8 # MIPS64: dmfc0 $12, $16, 2 # encoding: [0x40,0x2c,0x80,0x02]
9 # MIPS64: dmfc0 $12, $16, 0 # encoding: [0x40,0x2c,0x80,0x00]
10 # MIPS64: mfc0 $12, $16, 2 # encoding: [0x40,0x0c,0x80,0x02]
11 # MIPS64: mfc0 $12, $16, 0 # encoding: [0x40,0x0c,0x80,0x00
[all...] |
| /external/valgrind/VEX/auxprogs/ |
| genoffsets.c | 230 // MIPS64
231 GENOFFSET(MIPS64,mips64,r0);
232 GENOFFSET(MIPS64,mips64,r1);
233 GENOFFSET(MIPS64,mips64,r2);
234 GENOFFSET(MIPS64,mips64,r3);
235 GENOFFSET(MIPS64,mips64,r4)
[all...] |
| /external/v8/src/mips64/ |
| frames-mips64.cc | 9 #include "src/mips64/assembler-mips64-inl.h"
10 #include "src/mips64/assembler-mips64.h"
11 #include "src/mips64/frames-mips64.h"
|
| /external/llvm/test/CodeGen/Mips/ |
| octeon_popcnt.ll | 1 ; RUN: llc -O1 -march=mips64 -mcpu=octeon < %s | FileCheck %s -check-prefix=OCTEON
2 ; RUN: llc -O1 -march=mips64 -mcpu=mips64 < %s | FileCheck %s -check-prefix=MIPS64
10 ; MIPS64-LABEL: cnt8:
11 ; MIPS64-NOT: pop
20 ; MIPS64-LABEL: cnt16:
21 ; MIPS64-NOT: pop
30 ; MIPS64-LABEL: cnt32:
31 ; MIPS64-NOT: po
[all...] |
| cttz-v.ll | 2 ; RUN: llc < %s -march=mips64el -mcpu=mips64r2 | FileCheck %s -check-prefix=MIPS64
21 ; MIPS64-DAG: sll $[[A0:[0-9]+]], $4, 0
22 ; MIPS64-DAG: addiu $[[R0:[0-9]+]], $[[A0]], -1
23 ; MIPS64-DAG: not $[[R1:[0-9]+]], $[[A0]]
24 ; MIPS64-DAG: and $[[R2:[0-9]+]], $[[R1]], $[[R0]]
25 ; MIPS64-DAG: clz $[[R3:[0-9]+]], $[[R2]]
26 ; MIPS64-DAG: addiu $[[R4:[0-9]+]], $zero, 32
27 ; MIPS64-DAG: subu $2, $[[R4]], $[[R3]]
28 ; MIPS64-DAG: sll $[[A1:[0-9]+]], $5, 0
29 ; MIPS64-DAG: addiu $[[R5:[0-9]+]], $[[A1]], -
[all...] |
| octeon.ll | 1 ; RUN: llc -O1 < %s -march=mips64 -mcpu=octeon | FileCheck %s -check-prefixes=ALL,OCTEON
2 ; RUN: llc -O1 < %s -march=mips64 -mcpu=mips64 | FileCheck %s -check-prefixes=ALL,MIPS64
9 ; MIPS64: daddu $[[T0:[0-9]+]], $4, $5
10 ; MIPS64: jr $ra
11 ; MIPS64: andi $2, $[[T0]], 255
22 ; MIPS64: dmult $4, $5
23 ; MIPS64: jr $ra
24 ; MIPS64: mflo $
[all...] |
| ctlz-v.ll | 2 ; RUN: llc < %s -march=mips64el -mcpu=mips64r2 | FileCheck %s -check-prefix=MIPS64
11 ; MIPS64-DAG: sll $[[A0:[0-9]+]], $4, 0
12 ; MIPS64-DAG: clz $2, $[[A0]]
13 ; MIPS64-DAG: sll $[[A1:[0-9]+]], $5, 0
14 ; MIPS64-DAG: clz $3, $[[A1]]
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/mips/ |
| micromips@mips64.d | 2 #name: MIPS MIPS64 instructions
3 #source: mips64.s
6 # Check MIPS64 instruction assembly (microMIPS).
|
| mipsr6@mips64.d | 2 #name: MIPS MIPS64 instructions
4 #source: mips64.s
6 # Check MIPS64 instruction assembly
|
| elf_arch_mips64.d | 1 # name: ELF MIPS64 markings
4 # as: -32 -march=mips64
7 private flags = 6.......: .*\[mips64\].*
11 ISA: MIPS64
|
| mips64.d | 2 #name: MIPS MIPS64 instructions
5 # Check MIPS64 instruction assembly
|
| /build/make/target/board/generic_mips64/ |
| system.prop | 2 # system.prop for generic mips64 sdk
|
| /external/valgrind/coregrind/m_gdbserver/ |
| mips64-linux-valgrind.xml | 11 <xi:include href="mips64-cpu.xml"/>
12 <xi:include href="mips64-cp0.xml"/>
13 <xi:include href="mips64-fpu.xml"/>
14 <xi:include href="mips64-cpu-valgrind-s1.xml"/>
15 <xi:include href="mips64-cp0-valgrind-s1.xml"/>
16 <xi:include href="mips64-fpu-valgrind-s1.xml"/>
17 <xi:include href="mips64-cpu-valgrind-s2.xml"/>
18 <xi:include href="mips64-cp0-valgrind-s2.xml"/>
19 <xi:include href="mips64-fpu-valgrind-s2.xml"/>
|
| /system/core/libpixelflinger/tests/arch-mips64/col32cb16blend/ |
| Android.mk | 6 ../../../arch-mips64/col32cb16blend.S
12 LOCAL_MODULE:= test-pixelflinger-mips64-col32cb16blend
|
| /external/llvm/test/CodeGen/Mips/cstmaterialization/ |
| stack.ll | 2 ; RUN: llc -march=mips64el -mcpu=mips64 < %s | \
3 ; RUN: FileCheck %s -check-prefix=CHECK-MIPS64
4 ; RUN: llc -march=mipsel -mcpu=mips64 -target-abi n32 < %s | \
27 ; CHECK-MIPS64: lui $[[R0:[0-9]+]], 1
28 ; CHECK-MIPS64: daddiu $[[R0]], $[[R0]], 32
29 ; CHECK-MIPS64: dsubu $sp, $sp, $[[R0]]
35 ; CHECK-MIPS64: lui
36 ; CHECK-MIPS64: lui
37 ; CHECK-MIPS64: lui
38 ; CHECK-MIPS64: lu
[all...] |
