| /external/llvm/test/CodeGen/Mips/llvm-ir/ |
| select-flt.ll | 40 ; M2: mtc1 $6, $f0
44 ; M2: mtc1 $5, $f0
47 ; CMOV-32: mtc1 $6, $f0
48 ; CMOV-32: mtc1 $5, $f1
52 ; SEL-32: mtc1 $5, $[[F0:f[0-9]+]]
53 ; SEL-32: mtc1 $6, $[[F1:f[0-9]+]]
54 ; SEL-32: mtc1 $4, $f0
61 ; SEL-64: mtc1 $4, $f0
64 ; MM32R3: mtc1 $6, $[[F0:f[0-9]+]]
65 ; MM32R3: mtc1 $5, $[[F1:f[0-9]+]
[all...] |
| select-dbl.ll | 43 ; M2: mtc1 $7, $f0
45 ; M2: mtc1 $6, $f1
47 ; CMOV-32: mtc1 $7, $[[F0:f[0-9]+]]
48 ; CMOV-32R1: mtc1 $6, $f{{[0-9]+}}
54 ; SEL-32: mtc1 $7, $[[F0:f[0-9]+]]
57 ; SEL-32: mtc1 $4, $f0
72 ; SEL-64: mtc1 $4, $f0
75 ; MM32R3: mtc1 $7, $[[F0:f[0-9]+]]
105 ; SEL-32: mtc1 $[[T0]], $f0
120 ; SEL-64: mtc1 $6, $f
[all...] |
| ret.ll | 162 ; NO-MTHC1-DAG: mtc1 $zero, $f0
164 ; MTHC1-DAG: mtc1 $zero, $f0
192 ; NO-MTHC1-DAG: mtc1 $zero, $f0
193 ; NO-MTHC1-DAG: mtc1 $zero, $f1
195 ; MTHC1-DAG: mtc1 $zero, $f0
|
| /external/llvm/test/CodeGen/Mips/ |
| analyzebranch.ll | 16 ; 32-GPR: mtc1 $zero, $[[Z:f[0-9]]]
49 ; GPR: mtc1 $zero, $[[Z:f[0-9]]]
|
| fcopysign-f32-f64.ll | 23 ; 64: mtc1 $[[OR]], $f0
27 ; 64R2: mtc1 $[[INS]], $f0
|
| hf16call32.ll | [all...] |
| selectcc.ll | 23 ; SOURCE-SCHED: mtc1
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/mips/ |
| mips-abi32.d | 68 e8: 44810800 mtc1 at,\$f1
69 ec: 44800000 mtc1 zero,\$f0
|
| mips-abi32.s | 73 # 00e8 mtc1 at,$f1
74 # 00ec mtc1 zero,$f0
|
| mips-gp32-fp32.d | 68 e8: 44810800 mtc1 at,\$f1
69 ec: 44800000 mtc1 zero,\$f0
|
| mips-gp32-fp32.s | 73 # 00e8 mtc1 at,$f1
74 # 00ec mtc1 zero,$f0
|
| relax-swap1.s | 118 mtc1 $2, $31
120 mtc1 $2, $31
|
| mips-abi32-pic.d | 88 138: 44810800 mtc1 at,\$f1
89 13c: 44800000 mtc1 zero,\$f0
|
| mips-abi32-pic.s | 114 # 0180 mtc1 at,$f1
115 # 0184 mtc1 zero,$f0
|
| /art/runtime/arch/mips/ |
| asm_support_mips.S | 90 mtc1 \reven, \feven
110 mtc1 \reven, \feven
111 mtc1 \rodd, \fodd
|
| /external/llvm/test/CodeGen/Mips/Fast-ISel/ |
| sel1.ll | 72 ; CHECK-DAG: mtc1 $6, $f0
73 ; CHECK-DAG: mtc1 $5, $f1
87 ; CHECK-DAG: mtc1 $6, $f2
|
| /external/swiftshader/third_party/LLVM/lib/Target/Mips/ |
| MipsExpandPseudo.cpp | 90 const MCInstrDesc& Mtc1Tdd = TII->get(Mips::MTC1);
95 // mtc1 Lo, $fp
96 // mtc1 Hi, $fp + 1
|
| /external/swiftshader/third_party/subzero/tests_lit/llvm2ice_tests/ |
| fp.load_store.ll | 66 ; MIPS32O2: mtc1 a1,$f{{.*}}
82 ; MIPS32O2: mtc1 a2,$f{{.*}}
83 ; MIPS32O2: mtc1 a3,$f{{.*}}
|
| fp_const_pool.ll | 32 ; MIPS32: mtc1 zero,[[REG:.*]]
36 ; MIPS32: mtc1 zero,[[REGLo:.*]]
37 ; MIPS32: mtc1 zero,[[REGHi:.*]]
|
| vector-mips.ll | 47 ; MIPS32: mtc1 a1,$f0
55 ; MIPS32: mtc1 a2,$f0
208 ; MIPS32: mtc1 a2,$f0
219 ; MIPS32: mtc1 v0,$f0
|
| /external/valgrind/none/tests/mips64/ |
| change_fp_mode.stdout.exp | 18 mtc1 $t0, $f0 :: lo32(f1): 5a5a, lo32(f0): 90abcdef
19 mtc1 $t0, $f1 :: lo32(f1): 90abcdef, lo32(f0): 5a5a
67 mtc1 $t0, $f0 :: lo32(f1): 5a5a, lo32(f0): 90abcdef
68 mtc1 $t0, $f1 :: lo32(f1): 90abcdef, lo32(f0): 5a5a
116 mtc1 $t0, $f0 :: lo32(f1): 5a5a, lo32(f0): 90abcdef
117 mtc1 $t0, $f1 :: lo32(f1): 90abcdef, lo32(f0): 5a5a
|
| macro_fpu.h | 117 "mtc1 %2, $f0" "\n\t" \
128 "mtc1 %2, $f0" "\n\t" \
224 "mtc1 $zero, $f0" "\n\t" \
272 "mtc1 $zero, $f0" "\n\t" \
|
| /external/libjpeg-turbo/simd/ |
| jsimd_mips_dspr2.S | [all...] |
| /external/llvm/test/CodeGen/Mips/cconv/ |
| arguments-hard-float-varargs.ll | 49 ; O32BE-DAG: mtc1 $5, [[FTMP1:\$f[0-9]*[02468]+]]
50 ; O32BE-DAG: mtc1 $4, [[FTMP2:\$f[0-9]*[13579]+]]
51 ; O32LE-DAG: mtc1 $4, [[FTMP1:\$f[0-9]*[02468]+]]
52 ; O32LE-DAG: mtc1 $5, [[FTMP2:\$f[0-9]*[13579]+]]
|
| /external/llvm/lib/Target/Mips/ |
| MipsSEInstrInfo.h | 101 /// MTC1 F4, A5
105 /// instruction between MTC1 and CVT_D32_W.
|
