| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/mips/ |
| mips-gp32-fp32-pic.d | 88 138: 44810800 mtc1 at,\$f1
89 13c: 44800000 mtc1 zero,\$f0
|
| mips-gp32-fp32-pic.s | 114 # 0180 mtc1 at,$f1
115 # 0184 mtc1 zero,$f0
|
| mips-gp64-fp32-pic.d | 88 134: 44810800 mtc1 at,\$f1
89 138: 44800000 mtc1 zero,\$f0
|
| mips-gp64-fp32-pic.s | 113 # 017c mtc1 at,$f1
114 # 0180 mtc1 zero,$f0
|
| mips-gp64-fp32.d | 63 d0: 44810800 mtc1 at,\$f1
64 d4: 44800000 mtc1 zero,\$f0
|
| mips-gp64-fp32.s | 67 # 00d0 mtc1 at,$f1
68 # 00d4 mtc1 zero,$f0
|
| micromips.s | [all...] |
| mxu.s | 109 mtc1 $2, $2
110 mtc1 $2, $f1
|
| relax-swap1-mips1.d | 265 0+0344 <[^>]*> mtc1 v0,\$f31
268 0+0350 <[^>]*> mtc1 v0,\$f31
|
| relax-swap1-mips2.d | 234 0+02c8 <[^>]*> mtc1 v0,\$f31
237 0+02d4 <[^>]*> mtc1 v0,\$f31
|
| /external/swiftshader/third_party/LLVM/lib/Target/Mips/ |
| MipsInstrFPU.td | 182 def MTC1 : FFRGPR<0x04, (outs FGR32:$fs), (ins CPURegs:$rt),
183 "mtc1\t$rt, $fs",
335 // This pseudo instr gets expanded into 2 mtc1 instrs after register
363 def : Pat<(f32 fpimm0), (MTC1 ZERO)>;
364 def : Pat<(f32 fpimm0neg), (FNEG_S (MTC1 ZERO))>;
366 def : Pat<(f32 (sint_to_fp CPURegs:$src)), (CVT_S_W (MTC1 CPURegs:$src))>;
367 def : Pat<(f64 (sint_to_fp CPURegs:$src)), (CVT_D32_W (MTC1 CPURegs:$src))>;
|
| /art/compiler/optimizing/ |
| emit_swap_mips_test.cc | 204 "mtc1 $t8, $f2\n";
222 "mtc1 $a0, $f4\n"
223 "mtc1 $a1, $f5\n"
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/iq2000/ |
| allinsn.s | 384 .global mtc1
385 mtc1: label
386 mtc1 %0,%0
|
| allinsn.d | 292 0000017c <mtc1>:
293 17c: 44 80 00 00 mtc1 r0,r0
|
| /external/llvm/test/CodeGen/Mips/Fast-ISel/ |
| overflt.ll | 19 ; CHECK: mtc1 $[[REG_FPCONST_INT]], $f[[REG_FPCONST:[0-9]+]]
|
| /external/llvm/test/CodeGen/Mips/cconv/ |
| arguments-hard-float.ll | 178 ; O32LE-DAG: mtc1 $6, [[F1:\$f[0-9]*[02468]+]]
179 ; O32LE-DAG: mtc1 $7, [[F2:\$f[0-9]*[13579]+]]
180 ; O32BE-DAG: mtc1 $6, [[F2:\$f[0-9]*[13579]+]]
181 ; O32BE-DAG: mtc1 $7, [[F1:\$f[0-9]*[02468]+]]
|
| /external/llvm/lib/Target/Mips/ |
| MipsSEInstrInfo.cpp | 118 Opc = Mips::MTC1;
369 expandCvtFPInt(MBB, MI, Mips::CVT_S_W, Mips::MTC1, false);
372 expandCvtFPInt(MBB, MI, Mips::CVT_D32_W, Mips::MTC1, false);
378 expandCvtFPInt(MBB, MI, Mips::CVT_D64_W, Mips::MTC1, true);
652 const MCInstrDesc& Mtc1Tdd = get(Mips::MTC1);
657 // mtc1 Lo, $fp
665 // mtc1 Lo, $fp
666 // mtc1 Hi, $fp + 1
|
| MicroMipsInstrFPU.td | 109 def MTC1_MM : MMRel, MTC1_FT<"mtc1", FGR32Opnd, GPR32Opnd,
|
| /external/valgrind/none/tests/mips64/ |
| move_instructions.c | 57 "mtc1 $t0, $f0" "\n\t" \
67 printf("mtc1, mov.s, mfc1 :: mem: 0x%llx out: 0x%llx\n", \
99 "mtc1 $t0, $f0" "\n\t" \
100 "mtc1 $t1, $f2" "\n\t" \
123 "mtc1 $t0, $f0" "\n\t" \
124 "mtc1 $t1, $f2" "\n\t" \
|
| /external/swiftshader/third_party/subzero/tests_lit/llvm2ice_tests/ |
| vector-select.ll | 913 ; MIPS32: mtc1 [[T2]],$f0
914 ; MIPS32: mtc1 [[T6]],$f1
918 ; MIPS32: mtc1 [[T3]],$f0
919 ; MIPS32: mtc1 [[T7]],[[T11]]
923 ; MIPS32: mtc1 [[T4]],$f0
924 ; MIPS32: mtc1 [[T8]],[[T11]]
928 ; MIPS32: mtc1 [[T5]],$f0
929 ; MIPS32: mtc1 [[T9]],[[T11]]
|
| /external/valgrind/none/tests/mips32/ |
| round.c | 117 __asm__ volatile("mtc1 %2, $f0" "\n\t" \
126 __asm__ volatile("mtc1 %2, $f0" "\n\t" \
|
| /external/llvm/test/CodeGen/Mips/msa/ |
| basic_operations_float.ll | 152 ; ALL-NOT: mtc1
212 ; ALL-NOT: mtc1
232 ; ALL-NOT: mtc1
|
| /external/llvm/test/MC/Mips/ |
| micromips-fpu-instructions.s | 55 # CHECK-EL: mtc1 $6, $f8 # encoding: [0xc8,0x54,0x3b,0x28]
120 # CHECK-EB: mtc1 $6, $f8 # encoding: [0x54,0xc8,0x28,0x3b]
181 mtc1 $6, $f8
|
| /external/valgrind/VEX/priv/ |
| guest_mips_helpers.c | 473 "mtc1 %1, $f20" "\n\t" \
519 "mtc1 %1, $f20" "\n\t" \
520 "mtc1 %2, $f22" "\n\t" \
|
| /toolchain/binutils/binutils-2.25/cpu/ |
| iq2000m.cpu | 354 (dni mtc1 "move to coprocessor 1" (MACH2000 USES-RT)
355 "mtc1 $rt,$rd"
357 (unimp mtc1)
|
