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  /external/mesa3d/src/egl/wayland/wayland-drm/
wayland-drm.xml 130 <arg name="offset0" type="int"/>
175 <arg name="offset0" type="int"/>
  /external/mesa3d/src/gallium/auxiliary/gallivm/
lp_bld_sample_aos.c 270 * \param offset0 resulting relative offset for coord0
286 LLVMValueRef *offset0,
298 * way to calculate offset1 relative to offset0. Instead, compute them
299 * independently. Otherwise, try to compute offset0 and offset1 with
355 offset0, i0);
384 *offset0 = lp_build_mul(int_coord_bld, coord0, stride);
386 lp_build_add(int_coord_bld, *offset0, stride),
406 *offset0 = lp_build_mul(int_coord_bld, coord0, stride);
408 *offset0,
420 *offset0 = int_coord_bld->zero
    [all...]
  /external/llvm/test/CodeGen/AMDGPU/
ds_write2.ll 183 ; SI: ds_write2_b32 [[BASEADDR:v[0-9]+]], [[VAL1:v[0-9]+]], [[VAL1]] offset0:8 offset1:27
212 ; SI: ds_write2_b32 [[BASEADDR:v[0-9]+]], [[VAL0:v[0-9]+]], [[VAL0]] offset0:3 offset1:11
213 ; SI: ds_write2_b32 [[BASEADDR:v[0-9]+]], [[VAL1:v[0-9]+]], [[VAL1]] offset0:8 offset1:27
289 ; SI: ds_write2_b32 [[VPTR]], v[[VAL0]], v[[VAL1]] offset0:14 offset1:15
349 ; SI-DAG: ds_write2_b32 [[ZERO]], v{{[0-9]+}}, v{{[0-9]+}} offset0:2 offset1:3
410 ; CI: ds_write2_b32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} offset0:3 offset1:2{{$}}
411 ; CI: ds_write2_b32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} offset0:1{{$}}
ds_read2st64.ll 27 ; SI: ds_read2st64_b32 v{{\[}}[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:1 offset1:2
47 ; SI: ds_read2st64_b32 v{{\[}}[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:255 offset1:1
139 ; SI: ds_read2st64_b64 v{{\[}}[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:1 offset1:2
162 ; SI: ds_read2_b32 v{{\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}} offset0:128 offset1:129
179 ; SI: ds_read2st64_b64 v{{\[}}[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:127 offset1:4
ds_write2st64.ll 26 ; SI: ds_write2st64_b32 [[VPTR]], [[VAL0]], [[VAL1]] offset0:2 offset1:5
67 ; SI: ds_write2st64_b64 [[VPTR]], [[VAL0]], [[VAL1]] offset0:4 offset1:127
ds-negative-offset-addressing-mode-loop.ll 23 ; CI-DAG: ds_read2_b32 v{{\[[0-9]+:[0-9]+\]}}, [[VADDR]] offset0:32 offset1:34
local-memory-two-objects.ll 53 ; CI: ds_read2_b32 {{v\[[0-9]+:[0-9]+\]}}, [[SUB]] offset0:3 offset1:7
ds_read2.ll 67 ; SI: ds_read2_b32 v{{\[[0-9]+:[0-9]+\]}}, [[BASEADDR]] offset0:11 offset1:27
99 ; SI: ds_read2_b32 v{{\[[0-9]+:[0-9]+\]}}, [[BASEADDR]] offset0:11 offset1:27
133 ; SI: ds_read2_b32 v{{\[[0-9]+:[0-9]+\]}}, [[BASEADDR:v[0-9]+]] offset0:2 offset1:8
134 ; SI: ds_read2_b32 v{{\[[0-9]+:[0-9]+\]}}, [[BASEADDR]] offset0:11 offset1:27
368 ; SI: ds_read2_b32 v{{\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}} offset0:14 offset1:15
412 ; SI: ds_read2_b32 v{{\[[0-9]+:[0-9]+\]}}, [[ZERO]] offset0:2 offset1:3
si-triv-disjoint-mem-access.ll 13 ; CI: ds_read2_b32 {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}} offset0:1 offset1:3
158 ; CI: ds_read2_b32 {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}} offset0:100 offset1:102
ds-sub-offset.ll 97 ; GCN: ds_write2_b32 [[NEG]], {{v[0-9]+}}, {{v[0-9]+}} offset0:254 offset1:255
salu-to-valu.ll 174 ; GCN-NOHSA: s_mov_b32 [[OFFSET0:s[0-9]+]], 0x9a40{{$}}
176 ; GCN-NOHSA: buffer_load_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, s[{{[0-9]+:[0-9]+}}], [[OFFSET0]] addr64{{$}}
207 ; GCN-NOHSA-DAG: s_mov_b32 [[OFFSET0:s[0-9]+]], 0x13480{{$}}
208 ; GCN-NOHSA-DAG: buffer_load_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, s[{{[0-9]+:[0-9]+}}], [[OFFSET0]] addr64{{$}}
  /external/deqp/external/vulkancts/modules/vulkan/geometry/
vktGeometryInputGeometryShaderTests.cpp 196 << " const highp vec4 offset0 = vec4(-0.07, -0.01, 0.0, 0.0);\n"
205 src << " gl_Position = gl_in[ndx].gl_Position + offset0 + yoffset;\n"
  /external/llvm/lib/Target/AMDGPU/
VIInstrFormats.td 20 bits<8> offset0;
23 let Inst{7-0} = offset0;
SIInstrInfo.cpp 94 int64_t &Offset0,
127 Offset0 = cast<ConstantSDNode>(Load0->getOperand(2))->getZExtValue();
151 Offset0 = Load0Offset->getZExtValue();
185 Offset0 = cast<ConstantSDNode>(Off0)->getZExtValue();
223 // The 2 offset instructions use offset0 and offset1 instead. We can treat
227 getNamedOperand(LdSt, AMDGPU::OpName::offset0);
231 uint8_t Offset0 = Offset0Imm->getImm();
234 if (Offset1 > Offset0 && Offset1 - Offset0 == 1) {
253 Offset = EltSize * Offset0;
    [all...]
AMDGPUISelDAGToDAG.cpp 90 bool SelectDS64Bit4ByteAligned(SDValue Ptr, SDValue &Base, SDValue &Offset0,
719 SDValue &Offset0,
732 Offset0 = CurDAG->getTargetConstant(DWordOffset0, DL, MVT::i8);
758 Offset0 = CurDAG->getTargetConstant(DWordOffset0, DL, MVT::i8);
775 Offset0 = CurDAG->getTargetConstant(DWordOffset0, DL, MVT::i8);
783 Offset0 = CurDAG->getTargetConstant(0, DL, MVT::i8);
    [all...]
SIInstrInfo.td 542 def offset0 : NamedOperandU8<"Offset0", NamedMatchClass<"Offset0">>;
    [all...]
SIInstrFormats.td 491 bits<8> offset0;
494 let Inst{7-0} = offset0;
  /external/llvm/test/CodeGen/SPARC/
64abi.ll 504 ; HARD-DAG: std %f4, [%sp+[[Offset0:[0-9]+]]]
506 ; HARD-DAG: ldx [%sp+[[Offset0]]], %o2
519 ; HARD: st %f1, [%fp+[[Offset0:[0-9]+]]]
524 ; HARD: ld [%fp+[[Offset0]]], %f1
  /development/tools/bugreport/src/com/android/bugreport/html/
Renderer.java 338 hdf.setValue("offset0", Integer.toString(f.offset0));
  /development/tools/bugreport/src/com/android/bugreport/stacks/
ThreadSnapshotParser.java 196 frame.offset0 = Integer.parseInt(kernelRe.group(3), 16);
315 + " / 0x" + kf.offset0 + " / 0x" + kf.offset1);
  /system/libufdt/
ufdt_overlay.c 261 * "/path/to/node:prop:offset0\x00/path/to/node:prop:offset1..."
443 * <offset0 offset1 offset2 ...>
  /external/llvm/test/MC/Disassembler/AMDGPU/
ds_vi.txt 6 # VI: ds_write2_b32 v2, v4, v6 offset0:4 ; encoding: [0x04,0x00,0x1c,0xd8,0x02,0x04,0x06,0x00]
9 # VI: ds_write2_b32 v2, v4, v6 offset0:4 offset1:8 ; encoding: [0x04,0x08,0x1c,0xd8,0x02,0x04,0x06,0x00]
15 # VI: ds_read2_b32 v[8:9], v2 offset0:4 ; encoding: [0x04,0x00,0x6e,0xd8,0x02,0x00,0x00,0x08]
18 # VI: ds_read2_b32 v[8:9], v2 offset0:4 offset1:8 ; encoding: [0x04,0x08,0x6e,0xd8,0x02,0x00,0x00,0x08]
  /frameworks/rs/cpu_ref/
rsCpuIntrinsics_neon_3DLUT.S 137 * r6 = offset0
  /hardware/intel/common/libva/va/wayland/protocol/
wayland-drm.xml 130 <arg name="offset0" type="int"/>
  /external/aac/libSBRdec/src/
sbrdecoder.cpp 1337 INT strideIn, strideOut, offset0, offset1; local
    [all...]

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