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  /external/llvm/test/CodeGen/AMDGPU/
fminnum.ll 3 ; RUN: llc -march=r600 -mcpu=cypress < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
image-attributes.ll 1 ; RUN: llc -march=r600 -mcpu=juniper < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
load-constant-i32.ll 4 ; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
max.ll 2 ; RUN: llc -march=r600 -mcpu=cypress < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
sdivrem24.ll 3 ; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
setcc-opt.ll 3 ; RUN: llc -march=r600 -mcpu=cypress -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
setcc64.ll 4 ; XXX: Merge this into setcc, once R600 supports 64-bit operations
sminmax.ll 3 ; RUN: llc -march=r600 -mcpu=cypress -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
udivrem.ll 3 ; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck --check-prefix=EG --check-prefix=FUNC %s
udivrem24.ll 3 ; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
load-global-i8.ll 4 ; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
5 ; RUN: llc -march=r600 -mcpu=cayman < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
  /external/llvm/test/Transforms/LoopVectorize/
runtime-check-address-space.ll 1 ; RUN: opt -S -march=r600 -mcpu=cayman -basicaa -loop-vectorize -force-vector-interleave=1 -force-vector-width=4 -dce -instcombine < %s | FileCheck %s
  /external/mesa3d/src/amd/addrlib/
addrinterface.cpp 820 * FP16 can be reported as EXPORT_NORM for rv770 in r600
addrtypes.h 166 * R600/R800 tiling mode can be cast to hw enums directly but never cast into HW enum from
  /external/mesa3d/src/gallium/drivers/r600/
evergreen_compute.c 175 /* We need to define these R600 registers here, because we can't include
198 /* R600 / R700 */
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  /external/mesa3d/src/gallium/drivers/radeon/
r600_texture.c 621 /* Overallocate FMASK on R600-R700 to fix colorbuffer corruption.
623 * for R600-R700 asics. */
805 if (rscreen->chip_class == R600 &&
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  /prebuilts/clang/host/darwin-x86/clang-4053586/prebuilt_include/llvm/include/llvm/IR/
Intrinsics.gen     [all...]
  /prebuilts/clang/host/linux-x86/clang-4053586/prebuilt_include/llvm/include/llvm/IR/
Intrinsics.gen     [all...]
  /external/llvm/lib/Target/AMDGPU/
R600ISelLowering.cpp 1 //===-- R600ISelLowering.cpp - R600 DAG Lowering Implementation -----------===//
11 /// \brief Custom DAG lowering for R600
812 // FIXME: Should be renamed to r600 prefix
818 // XXX - I'm assuming SI's RSQ_LEGACY matches R600's behavior.
    [all...]
R600Instructions.td 1 //===-- R600Instructions.td - R600 Instruction defs -------*- tablegen -*-===//
10 // TableGen definitions for instructions which are available on R600 family
372 // R600 SDNodes
680 // Common Instructions R600, R700, Evergreen, Cayman
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  /external/swiftshader/third_party/llvm-subzero/build/Android/include/llvm/IR/
Intrinsics.gen     [all...]
  /external/swiftshader/third_party/llvm-subzero/build/Linux/include/llvm/IR/
Intrinsics.gen     [all...]
  /external/swiftshader/third_party/llvm-subzero/build/MacOS/include/llvm/IR/
Intrinsics.gen     [all...]
  /external/swiftshader/third_party/llvm-subzero/build/Windows/include/llvm/IR/
Intrinsics.gen     [all...]
  /system/extras/simpleperf/scripts/bin/android/x86/
simpleperf 

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