| /toolchain/binutils/binutils-2.25/cpu/ |
| iq2000.cpu | 266 (("SLL" 0) ("SLMV" 1) ("SRL" 2) ("SRA" 3) ("SLLV" 4) ("SRMV" 5) ("SRLV" 6) ("SRAV" 7)
611 "sllv ${rd-rt},$rs"
616 (dni sllv "shift left logical variable" (USES-RD USES-RS USES-RT)
617 "sllv $rd,$rt,$rs"
[all...] |
| /external/llvm/test/MC/Mips/mips4/ |
| valid.s | 211 sll $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04]
212 sllv $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04]
|
| /external/llvm/test/MC/Mips/mips5/ |
| valid.s | 212 sll $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04]
213 sllv $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04]
|
| /external/llvm/test/MC/Mips/mips64/ |
| valid.s | 230 sll $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04]
231 sllv $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04]
|
| /external/llvm/test/MC/Mips/mips64r2/ |
| valid.s | 256 sll $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04]
257 sllv $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04]
|
| /external/llvm/test/MC/Mips/mips64r3/ |
| valid.s | 256 sll $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04]
257 sllv $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04]
|
| /external/llvm/test/MC/Mips/mips64r5/ |
| valid.s | 257 sll $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04]
258 sllv $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04]
|
| /external/swiftshader/third_party/subzero/src/ |
| IceAssemblerMIPS32.h | 261 void sllv(const Operand *OpRd, const Operand *OpRt, const Operand *OpRs);
|
| /external/swiftshader/third_party/subzero/tests_lit/llvm2ice_tests/ |
| 64bit.pnacl.ll | 567 ; MIPS32: sllv [[T1:.*]],[[A_HI:.*]],[[B_LO:.*]]
572 ; MIPS32: sllv [[T_LO:.*]],[[A_LO]],[[B_LO]]
603 ; MIPS32-O2: sllv
634 ; MIPS32: sllv [[T1:.*]],[[A_HI:.*]],[[B_LO:.*]]
639 ; MIPS32: sllv [[T_LO:.*]],[[A_LO]],[[B_LO]]
680 ; MIPS32: sllv [[T4:.*]],[[T3]],[[T2]]
720 ; MIPS32-O2: sllv
756 ; MIPS32: sllv [[T4:.*]],[[T3]],[[T2]]
794 ; MIPS32-O2: sllv
[all...] |
| arith.ll | 282 ; MIPS32: sllv {{.*}},{{.*}},[[REG]]
|
| /prebuilts/go/darwin-x86/src/runtime/ |
| sys_linux_mips64x.s | 236 SLLV $32, RSB
|
| /prebuilts/go/linux-x86/src/runtime/ |
| sys_linux_mips64x.s | 236 SLLV $32, RSB
|
| /external/llvm/test/MC/Disassembler/Mips/mips2/ |
| valid-mips2.txt | 44 0x01 0x20 0x38 0x04 # CHECK: sllv $7, $zero, $9
45 0x01 0x20 0x38 0x04 # CHECK: sllv $7, $zero, $9
|
| /external/llvm/test/MC/Disassembler/Mips/mips3/ |
| valid-mips3-el.txt | 156 0x04 0x38 0x20 0x01 # CHECK: sllv $7, $zero, $9
157 0x04 0x38 0x20 0x01 # CHECK: sllv $7, $zero, $9
|
| valid-mips3.txt | 65 0x01 0x20 0x38 0x04 # CHECK: sllv $7, $zero, $9
66 0x01 0x20 0x38 0x04 # CHECK: sllv $7, $zero, $9
|
| /external/llvm/test/MC/Disassembler/Mips/mips4/ |
| valid-mips4-el.txt | 175 0x04 0x38 0x20 0x01 # CHECK: sllv $7, $zero, $9
176 0x04 0x38 0x20 0x01 # CHECK: sllv $7, $zero, $9
|
| /toolchain/binutils/binutils-2.25/opcodes/ |
| iq2000-desc.c | 585 /* sllv ${rd-rt},$rs */
587 -1, "sllv2", "sllv", 32,
590 /* sllv $rd,$rt,$rs */
592 IQ2000_INSN_SLLV, "sllv", "sllv", 32,
[all...] |
| /external/llvm/test/MC/Disassembler/Mips/mips32/ |
| valid-mips32.txt | 54 0x00 0xa3 0x10 0x04 # CHECK: sllv $2, $3, $5
75 0x01 0x20 0x38 0x04 # CHECK: sllv $7, $zero, $9
76 0x01 0x20 0x38 0x04 # CHECK: sllv $7, $zero, $9
|
| /external/llvm/test/MC/Disassembler/Mips/mips32r2/ |
| valid-mips32r2.txt | 58 0x00 0xa3 0x10 0x04 # CHECK: sllv $2, $3, $5
80 0x01 0x20 0x38 0x04 # CHECK: sllv $7, $zero, $9
81 0x01 0x20 0x38 0x04 # CHECK: sllv $7, $zero, $9
|
| /external/llvm/test/MC/Disassembler/Mips/mips32r3/ |
| valid-mips32r3.txt | 55 0x00 0xa3 0x10 0x04 # CHECK: sllv $2, $3, $5
77 0x01 0x20 0x38 0x04 # CHECK: sllv $7, $zero, $9
78 0x01 0x20 0x38 0x04 # CHECK: sllv $7, $zero, $9
|
| /external/llvm/test/MC/Disassembler/Mips/mips32r5/ |
| valid-mips32r5.txt | 55 0x00 0xa3 0x10 0x04 # CHECK: sllv $2, $3, $5
77 0x01 0x20 0x38 0x04 # CHECK: sllv $7, $zero, $9
78 0x01 0x20 0x38 0x04 # CHECK: sllv $7, $zero, $9
|
| /external/llvm/test/MC/Disassembler/Mips/mips64/ |
| valid-mips64.txt | 74 0x00 0xa3 0x10 0x04 # CHECK: sllv $2, $3, $5
97 0x01 0x20 0x38 0x04 # CHECK: sllv $7, $zero, $9
98 0x01 0x20 0x38 0x04 # CHECK: sllv $7, $zero, $9
|
| /external/llvm/lib/Target/Mips/ |
| MipsScheduleP5600.td | 176 // add, addi, addiu, addu, andi, ori, rotr, se[bh], sllv?, sr[al]v?, slt, sltu,
|
| /external/llvm/test/MC/Mips/micromips32r6/ |
| valid.s | 322 sllv $2, $3, $5 # CHECK: sllv $2, $3, $5 # encoding: [0x00,0x65,0x10,0x10]
327 sll $2, $3, $5 # CHECK: sllv $2, $3, $5 # encoding: [0x00,0x65,0x10,0x10]
330 sll $2, $3 # CHECK: sllv $2, $2, $3 # encoding: [0x00,0x43,0x10,0x10]
[all...] |
| /external/llvm/test/MC/Mips/micromips64r6/ |
| valid.s | 242 sllv $2, $3, $5 # CHECK: sllv $2, $3, $5 # encoding: [0x00,0x65,0x10,0x10]
247 sll $2, $3, $5 # CHECK: sllv $2, $3, $5 # encoding: [0x00,0x65,0x10,0x10]
250 sll $2, $3 # CHECK: sllv $2, $2, $3 # encoding: [0x00,0x43,0x10,0x10]
|
