| /external/mesa3d/src/gallium/drivers/r300/compiler/ |
| radeon_compiler.c | 125 if (inst->U.I.SrcReg[i].File == RC_FILE_INPUT)
126 c->Program.InputsRead |= 1 << inst->U.I.SrcReg[i].Index;
151 if (inst->U.I.SrcReg[i].File == RC_FILE_INPUT && inst->U.I.SrcReg[i].Index == input) {
152 inst->U.I.SrcReg[i].File = new_input.File;
153 inst->U.I.SrcReg[i].Index = new_input.Index;
154 inst->U.I.SrcReg[i].Swizzle = combine_swizzles(new_input.Swizzle, inst->U.I.SrcReg[i].Swizzle);
155 if (!inst->U.I.SrcReg[i].Abs) {
156 inst->U.I.SrcReg[i].Negate ^= new_input.Negate
[all...] |
| radeon_emulate_branches.c | 79 inst_mov->U.I.SrcReg[0] = inst->U.I.SrcReg[0];
81 inst->U.I.SrcReg[0].File = RC_FILE_TEMPORARY;
82 inst->U.I.SrcReg[0].Index = inst_mov->U.I.DstReg.Index;
83 inst->U.I.SrcReg[0].Swizzle = 0;
84 inst->U.I.SrcReg[0].Abs = 0;
85 inst->U.I.SrcReg[0].Negate = 0;
169 inst_mov->U.I.SrcReg[0].File = RC_FILE_TEMPORARY;
170 inst_mov->U.I.SrcReg[0].Index = index;
188 inst_cmp->U.I.SrcReg[0] = inst_if->U.I.SrcReg[0]
[all...] |
| radeon_vert_fc.c | 131 new_inst->U.I.SrcReg[0].Index = 0;
132 new_inst->U.I.SrcReg[0].File = RC_FILE_NONE;
133 new_inst->U.I.SrcReg[0].Swizzle = RC_SWIZZLE_0000;
141 build_pred_src(&new_inst->U.I.SrcReg[0], fc_state);
151 new_inst->U.I.SrcReg[1].Index = 0;
152 new_inst->U.I.SrcReg[1].File = RC_FILE_NONE;
153 new_inst->U.I.SrcReg[1].Swizzle = RC_SWIZZLE_0000;
165 inst->U.I.SrcReg[0].Index = 0;
166 inst->U.I.SrcReg[0].File = RC_FILE_NONE;
167 inst->U.I.SrcReg[0].Swizzle = RC_SWIZZLE_0000
[all...] |
| radeon_emulate_loops.c | 100 if(!rc_src_reg_is_immediate(value->C, inst->U.I.SrcReg[0].File,
101 inst->U.I.SrcReg[0].Index)){
107 inst->U.I.SrcReg[0].Index,
108 inst->U.I.SrcReg[0].Swizzle,
109 inst->U.I.SrcReg[0].Negate, 0);
141 if(inst->U.I.SrcReg[0].File == RC_FILE_TEMPORARY &&
142 inst->U.I.SrcReg[0].Index == count_inst->Index &&
143 inst->U.I.SrcReg[0].Swizzle == count_inst->Swz){
145 } else if( inst->U.I.SrcReg[1].File == RC_FILE_TEMPORARY &&
146 inst->U.I.SrcReg[1].Index == count_inst->Index &
[all...] |
| radeon_program_print.c | 204 rc_print_register(f, inst.SrcReg[0].File,
205 inst.SrcReg[0].Index,inst.SrcReg[0].RelAddr);
208 rc_print_register(f, inst.SrcReg[1].File,
209 inst.SrcReg[1].Index,inst.SrcReg[1].RelAddr);
211 rc_print_register(f, inst.SrcReg[0].File,
212 inst.SrcReg[0].Index,inst.SrcReg[0].RelAddr);
215 rc_print_register(f, inst.SrcReg[1].File
[all...] |
| radeon_dataflow_swizzles.c | 49 if (GET_SWZ(inst->U.I.SrcReg[src].Swizzle, chan) != RC_SWIZZLE_UNUSED)
53 c->SwizzleCaps->Split(inst->U.I.SrcReg[src], usemask, &split);
64 mov->U.I.SrcReg[0] = inst->U.I.SrcReg[src];
70 SET_SWZ(mov->U.I.SrcReg[0].Swizzle, chan, RC_SWIZZLE_UNUSED);
72 phase_refmask |= 1 << GET_SWZ(mov->U.I.SrcReg[0].Swizzle, chan);
77 masked_negate = split.Phase[phase] & mov->U.I.SrcReg[0].Negate;
79 mov->U.I.SrcReg[0].Negate = 0;
81 mov->U.I.SrcReg[0].Negate = RC_MASK_XYZW;
85 inst->U.I.SrcReg[src].File = RC_FILE_TEMPORARY
[all...] |
| /external/llvm/lib/CodeGen/ |
| PHIEliminationUtils.h | 17 /// SrcReg when following the CFG edge to SuccMBB. This needs to be after
18 /// any def of SrcReg, but before any subsequent point where control flow
22 unsigned SrcReg);
|
| PHIEliminationUtils.cpp | 17 // findCopyInsertPoint - Find a safe place in MBB to insert a copy from SrcReg
19 // SrcReg, but before any subsequent point where control flow might jump out of
23 unsigned SrcReg) {
37 for (MachineInstr &RI : MRI.reg_instructions(SrcReg)) {
|
| RegisterCoalescer.h | 36 unsigned SrcReg;
41 /// The sub-register index of the old SrcReg in the new coalesced register.
50 /// True when DstReg and SrcReg are reversed from the original
56 /// SrcReg and DstReg.
61 : TRI(tri), DstReg(0), SrcReg(0), DstIdx(0), SrcIdx(0),
68 : TRI(tri), DstReg(PhysReg), SrcReg(VirtReg), DstIdx(0), SrcIdx(0),
75 /// Swap SrcReg and DstReg. Return false if swapping is impossible
103 unsigned getSrcReg() const { return SrcReg; }
108 /// Return the subregister index that SrcReg will be coalesced into, or 0.
|
| /external/swiftshader/third_party/LLVM/lib/CodeGen/ |
| PHIEliminationUtils.h | 17 /// SrcReg when following the CFG edge to SuccMBB. This needs to be after
18 /// any def of SrcReg, but before any subsequent point where control flow
22 unsigned SrcReg);
|
| PHIEliminationUtils.cpp | 17 // findCopyInsertPoint - Find a safe place in MBB to insert a copy from SrcReg
19 // SrcReg, but before any subsequent point where control flow might jump out of
23 unsigned SrcReg) {
37 for (MachineRegisterInfo::reg_iterator RI = MRI.reg_begin(SrcReg),
|
| RegisterCoalescer.h | 36 /// SrcReg - the virtual register that will be coalesced into dstReg.
37 unsigned SrcReg;
39 /// subReg_ - The subregister index of srcReg in DstReg. It is possible the
40 /// coalesce SrcReg into a subreg of the larger DstReg when DstReg is a
50 /// Flipped - True when DstReg and SrcReg are reversed from the oriignal
60 : TII(tii), TRI(tri), DstReg(0), SrcReg(0), SubIdx(0),
67 /// flip - Swap SrcReg and DstReg. Return false if swapping is impossible
95 unsigned getSrcReg() const { return SrcReg; }
97 /// getSubIdx - Return the subregister index in DstReg that SrcReg will be
|
| /external/llvm/lib/Target/ARM/ |
| Thumb1InstrInfo.cpp | 43 unsigned SrcReg, bool KillSrc) const {
48 assert(ARM::GPRRegClass.contains(DestReg, SrcReg) &&
51 if (st.hasV6Ops() || ARM::hGPRRegClass.contains(SrcReg)
54 .addReg(SrcReg, getKillRegState(KillSrc)));
64 .addReg(SrcReg, getKillRegState(KillSrc));
72 unsigned SrcReg, bool isKill, int FI,
76 (TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
77 isARMLowRegister(SrcReg))) && "Unknown regclass!");
80 (TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
81 isARMLowRegister(SrcReg))) {
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
| PPCInstrInfo.cpp | 304 unsigned DestReg, unsigned SrcReg,
307 if (PPC::GPRCRegClass.contains(DestReg, SrcReg))
309 else if (PPC::G8RCRegClass.contains(DestReg, SrcReg))
311 else if (PPC::F4RCRegClass.contains(DestReg, SrcReg))
313 else if (PPC::CRRCRegClass.contains(DestReg, SrcReg))
315 else if (PPC::VRRCRegClass.contains(DestReg, SrcReg))
317 else if (PPC::CRBITRCRegClass.contains(DestReg, SrcReg))
325 .addReg(SrcReg).addReg(SrcReg, getKillRegState(KillSrc));
327 BuildMI(MBB, I, DL, MCID, DestReg).addReg(SrcReg, getKillRegState(KillSrc))
[all...] |
| /external/mesa3d/src/mesa/program/ |
| prog_execute.c | 301 inst->SrcReg[0].File == PROGRAM_INPUT &&
302 inst->SrcReg[0].Index == VARYING_SLOT_TEX0 + inst->TexSrcUnit) {
304 GLuint attr = inst->SrcReg[0].Index;
405 fetch_vector4(&inst->SrcReg[0], machine, a);
416 fetch_vector4(&inst->SrcReg[0], machine, a);
417 fetch_vector4(&inst->SrcReg[1], machine, b);
433 fetch_vector4(&inst->SrcReg[0], machine, t);
481 fetch_vector4(&inst->SrcReg[0], machine, a);
482 fetch_vector4(&inst->SrcReg[1], machine, b);
483 fetch_vector4(&inst->SrcReg[2], machine, c)
[all...] |
| prog_instruction.c | 46 inst[i].SrcReg[0].File = PROGRAM_UNDEFINED;
47 inst[i].SrcReg[0].Swizzle = SWIZZLE_NOOP;
48 inst[i].SrcReg[1].File = PROGRAM_UNDEFINED;
49 inst[i].SrcReg[1].Swizzle = SWIZZLE_NOOP;
50 inst[i].SrcReg[2].File = PROGRAM_UNDEFINED;
51 inst[i].SrcReg[2].Swizzle = SWIZZLE_NOOP;
221 if (inst->SrcReg[i].File == inst->DstReg.File &&
222 inst->SrcReg[i].Index == inst->DstReg.Index) {
228 GLuint swizzle = GET_SWZ(inst->SrcReg[i].Swizzle, chan);
|
| prog_optimize.c | 107 const GLuint coord = GET_SWZ(inst->SrcReg[arg].Swizzle, comp);
133 src_comp = GET_SWZ(mov->SrcReg[0].Swizzle, comp);
218 if (inst->SrcReg[j].File == file) {
219 GLuint index = inst->SrcReg[j].Index;
221 inst->SrcReg[j].Index = map[index];
264 if (inst->SrcReg[j].File == PROGRAM_TEMPORARY) {
265 const GLuint index = inst->SrcReg[j].Index;
270 if (inst->SrcReg[j].RelAddr) {
277 const GLuint swz = GET_SWZ(inst->SrcReg[j].Swizzle, comp);
389 if (inst->SrcReg[j].RelAddr |
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonPeephole.cpp | 143 unsigned SrcReg = Src.getReg();
146 TargetRegisterInfo::isVirtualRegister(SrcReg)) {
150 PeepholeMap[DstReg] = SrcReg;
164 unsigned SrcReg = Src2.getReg();
165 PeepholeMap[DstReg] = SrcReg;
181 unsigned SrcReg = Src1.getReg();
183 std::make_pair(*&SrcReg, Hexagon::subreg_hireg);
192 unsigned SrcReg = Src.getReg();
195 TargetRegisterInfo::isVirtualRegister(SrcReg)) {
199 PeepholeMap[DstReg] = SrcReg;
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsSEInstrInfo.cpp | 82 unsigned SrcReg, bool KillSrc) const {
87 if (Mips::GPR32RegClass.contains(SrcReg)) {
92 } else if (Mips::CCRRegClass.contains(SrcReg))
94 else if (Mips::FGR32RegClass.contains(SrcReg))
96 else if (Mips::HI32RegClass.contains(SrcReg)) {
98 SrcReg = 0;
99 } else if (Mips::LO32RegClass.contains(SrcReg)) {
101 SrcReg = 0;
102 } else if (Mips::HI32DSPRegClass.contains(SrcReg))
104 else if (Mips::LO32DSPRegClass.contains(SrcReg))
[all...] |
| /external/mesa3d/src/gallium/drivers/svga/svgadump/ |
| svga_shader_dump.c | 417 static void dump_srcreg( struct sh_srcreg srcreg, struct sh_srcreg *indreg, const struct dump_info *di )
422 memcpy(&srcreg_sh, &srcreg, sizeof(srcreg_sh));
424 switch (srcreg.modifier) {
439 switch (srcreg.modifier) {
470 if (srcreg.swizzle_x != 0 || srcreg.swizzle_y != 1 || srcreg.swizzle_z != 2 || srcreg.swizzle_w != 3) {
472 if (srcreg.swizzle_x == srcreg.swizzle_y && srcreg.swizzle_y == srcreg.swizzle_z && srcreg.swizzle_z == srcreg.swizzle_w)
[all...] |
| /external/mesa3d/src/mesa/drivers/dri/i915/ |
| i915_fragprog.c | 285 GLuint coord = src_vector( p, &inst->SrcReg[0], program); \
302 (N<1)?0:src_vector( p, &inst->SrcReg[0], program), \
303 (N<2)?0:src_vector( p, &inst->SrcReg[1], program), \
304 (N<3)?0:src_vector( p, &inst->SrcReg[2], program)); \
338 if (inst->SrcReg[a].File == PROGRAM_TEMPORARY) {
341 if (inst->SrcReg[a].Index >= I915_MAX_TEMPORARY)
344 regsUsed |= 1 << inst->SrcReg[a].Index;
347 const unsigned field = GET_SWZ(inst->SrcReg[a].Swizzle, c);
350 live_components[inst->SrcReg[a].Index] |= (1U << field);
424 src0 = src_vector(p, &inst->SrcReg[0], program)
[all...] |
| /external/mesa3d/src/mesa/state_tracker/ |
| st_mesa_to_tgsi.c | 268 const struct prog_src_register *SrcReg )
270 struct ureg_src src = src_register( t, SrcReg->File, SrcReg->Index );
273 GET_SWZ( SrcReg->Swizzle, 0 ) & 0x3,
274 GET_SWZ( SrcReg->Swizzle, 1 ) & 0x3,
275 GET_SWZ( SrcReg->Swizzle, 2 ) & 0x3,
276 GET_SWZ( SrcReg->Swizzle, 3 ) & 0x3);
278 if (SrcReg->Negate == NEGATE_XYZW)
281 if (SrcReg->RelAddr) {
283 if (SrcReg->File != PROGRAM_INPUT &
[all...] |
| /external/mesa3d/src/mesa/drivers/dri/r200/ |
| r200_fragshader.c | 42 const struct atifragshader_src_register srcReg,
45 const GLuint index = srcReg.Index;
46 const GLuint srcmod = srcReg.argMod;
47 const GLuint srcrep = srcReg.argRep;
170 inst->SrcReg[optype][0], 1, &tfactor);
172 inst->SrcReg[optype][1], 2, &tfactor);
180 inst->SrcReg[optype][0], 2, &tfactor);
185 inst->SrcReg[optype][2], 2, &tfactor);
189 inst->SrcReg[optype][0], 0, &tfactor);
191 inst->SrcReg[optype][1], 1, &tfactor)
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/Blackfin/ |
| BlackfinInstrInfo.h | 51 unsigned DestReg, unsigned SrcReg,
56 unsigned SrcReg, bool isKill,
62 unsigned SrcReg, bool isKill,
|
| /external/swiftshader/third_party/LLVM/lib/Target/Alpha/ |
| AlphaInstrInfo.cpp | 123 unsigned DestReg, unsigned SrcReg,
125 if (Alpha::GPRCRegClass.contains(DestReg, SrcReg)) {
127 .addReg(SrcReg)
128 .addReg(SrcReg, getKillRegState(KillSrc));
129 } else if (Alpha::F4RCRegClass.contains(DestReg, SrcReg)) {
131 .addReg(SrcReg)
132 .addReg(SrcReg, getKillRegState(KillSrc));
133 } else if (Alpha::F8RCRegClass.contains(DestReg, SrcReg)) {
135 .addReg(SrcReg)
136 .addReg(SrcReg, getKillRegState(KillSrc))
[all...] |
