| /external/swiftshader/third_party/LLVM/lib/CodeGen/ |
| PeepholeOptimizer.cpp | 134 unsigned SrcReg, DstReg, SubIdx;
135 if (!TII->isCoalescableExtInstr(*MI, SrcReg, DstReg, SubIdx))
139 TargetRegisterInfo::isPhysicalRegister(SrcReg))
142 MachineRegisterInfo::use_nodbg_iterator UI = MRI->use_nodbg_begin(SrcReg);
162 UI = MRI->use_nodbg_begin(SrcReg);
235 const TargetRegisterClass *RC = MRI->getRegClass(SrcReg);
337 unsigned SrcReg;
339 if (!TII->AnalyzeCompare(MI, SrcReg, CmpMask, CmpValue) ||
340 TargetRegisterInfo::isPhysicalRegister(SrcReg))
344 if (TII->OptimizeCompareInstr(MI, SrcReg, CmpMask, CmpValue, MRI))
[all...] |
| TwoAddressInstructionPass.cpp | 393 unsigned &SrcReg, unsigned &DstReg,
395 SrcReg = 0;
399 SrcReg = MI.getOperand(1).getReg();
402 SrcReg = MI.getOperand(2).getReg();
406 IsSrcPhys = TargetRegisterInfo::isPhysicalRegister(SrcReg);
442 unsigned SrcReg, DstReg;
445 if (!isCopyToReg(*DefMI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys))
447 Reg = SrcReg;
484 unsigned SrcReg;
486 if (isCopyToReg(UseMI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys))
[all...] |
| PHIElimination.cpp | 175 unsigned SrcReg = MPhi->getOperand(i).getReg();
176 const MachineInstr *DefMI = MRI->getVRegDef(SrcReg);
285 unsigned SrcReg = MPhi->getOperand(i*2+1).getReg();
288 assert(TargetRegisterInfo::isVirtualRegister(SrcReg) &&
297 MachineInstr *DefMI = MRI->getVRegDef(SrcReg);
312 findPHICopyInsertPoint(&opBlock, &MBB, SrcReg);
317 TII->get(TargetOpcode::COPY), IncomingReg).addReg(SrcReg, 0, SrcSubReg);
334 bool ValueIsUsed = VRegPHIUseCount[BBVRegPair(opBlock.getNumber(), SrcReg)];
338 if (!ValueIsUsed && !LV->isLiveOut(SrcReg, opBlock)) {
346 if (Term != opBlock.end() && Term->readsRegister(SrcReg)) {
[all...] |
| OptimizePHIs.cpp | 100 unsigned SrcReg = MI->getOperand(i).getReg();
101 if (SrcReg == DstReg)
103 MachineInstr *SrcMI = MRI->getVRegDef(SrcReg);
121 SingleValReg = SrcReg;
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCFastISel.cpp | 160 bool PPCEmitStore(MVT VT, unsigned SrcReg, Address &Addr);
164 bool PPCEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
175 unsigned SrcReg, bool IsSigned);
176 unsigned PPCMoveToFPReg(MVT VT, unsigned SrcReg, bool IsSigned);
619 // Emit a store instruction to store SrcReg at Addr.
620 bool PPCFastISel::PPCEmitStore(MVT VT, unsigned SrcReg, Address &Addr) {
621 assert(SrcReg && "Nothing to store!");
625 const TargetRegisterClass *RC = MRI.getRegClass(SrcReg);
660 bool IsVSSRC = isVSSRCRegister(SrcReg);
661 bool IsVSFRC = isVSFRCRegister(SrcReg);
[all...] |
| PPCInstrInfo.cpp | 250 unsigned &SrcReg, unsigned &DstReg,
256 SrcReg = MI.getOperand(1).getReg();
843 unsigned SrcReg, bool KillSrc) const {
848 PPC::VSRCRegClass.contains(SrcReg)) {
852 if (VSXSelfCopyCrash && SrcReg == SuperReg)
857 PPC::VSRCRegClass.contains(SrcReg)) {
861 if (VSXSelfCopyCrash && SrcReg == SuperReg)
865 } else if (PPC::F8RCRegClass.contains(SrcReg) &&
868 TRI->getMatchingSuperReg(SrcReg, PPC::sub_64, &PPC::VSRCRegClass);
873 SrcReg = SuperReg
[all...] |
| PPCInstrInfo.h | 72 unsigned SrcReg, bool isKill, int FrameIdx,
152 unsigned &SrcReg, unsigned &DstReg,
185 const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
190 unsigned SrcReg, bool isKill, int FrameIndex,
249 bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
252 bool optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg,
|
| /external/llvm/lib/Target/SystemZ/ |
| SystemZInstrInfo.cpp | 127 unsigned SrcReg = MI.getOperand(1).getReg();
129 bool SrcIsHigh = isHighReg(SrcReg);
133 emitGRX32Move(*MI.getParent(), MI, MI.getDebugLoc(), DestReg, SrcReg,
194 // Emit a zero-extending move from 32-bit GPR SrcReg to 32-bit GPR
195 // DestReg before MBBI in MBB. Use LowLowOpcode when both DestReg and SrcReg
197 // taken from the low end of SrcReg (8 for LLCR, 16 for LLHR and 32 for LR).
198 // KillSrc is true if this move is the last use of SrcReg.
202 unsigned SrcReg, unsigned LowLowOpcode,
206 bool SrcIsHigh = isHighReg(SrcReg);
215 .addReg(SrcReg, getKillRegState(KillSrc))
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonInstrInfo.cpp | 763 unsigned SrcReg, bool KillSrc) const {
767 if (Hexagon::IntRegsRegClass.contains(SrcReg, DestReg)) {
769 .addReg(SrcReg, KillFlag);
772 if (Hexagon::DoubleRegsRegClass.contains(SrcReg, DestReg)) {
774 .addReg(SrcReg, KillFlag);
777 if (Hexagon::PredRegsRegClass.contains(SrcReg, DestReg)) {
780 .addReg(SrcReg).addReg(SrcReg, KillFlag);
784 Hexagon::IntRegsRegClass.contains(SrcReg)) {
786 .addReg(SrcReg, KillFlag)
[all...] |
| /external/llvm/lib/Target/ARM/ |
| Thumb2InstrInfo.h | 43 const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
48 unsigned SrcReg, bool isKill, int FrameIndex,
|
| ARMBaseInstrInfo.cpp | 700 unsigned SrcReg, bool KillSrc,
713 MIB.addReg(SrcReg, getKillRegState(KillSrc));
723 unsigned SrcReg, bool KillSrc) const {
725 bool GPRSrc = ARM::GPRRegClass.contains(SrcReg);
729 .addReg(SrcReg, getKillRegState(KillSrc))));
734 bool SPRSrc = ARM::SPRRegClass.contains(SrcReg);
743 else if (ARM::DPRRegClass.contains(DestReg, SrcReg) && !Subtarget.isFPOnlySP())
745 else if (ARM::QPRRegClass.contains(DestReg, SrcReg))
750 MIB.addReg(SrcReg, getKillRegState(KillSrc));
752 MIB.addReg(SrcReg, getKillRegState(KillSrc))
[all...] |
| /external/llvm/lib/Target/AVR/ |
| AVRInstrInfo.cpp | 44 unsigned SrcReg, bool KillSrc) const {
47 if (AVR::GPR8RegClass.contains(DestReg, SrcReg)) {
49 } else if (AVR::DREGSRegClass.contains(DestReg, SrcReg)) {
51 } else if (SrcReg == AVR::SP && AVR::DREGSRegClass.contains(DestReg)) {
53 } else if (DestReg == AVR::SP && AVR::DREGSRegClass.contains(SrcReg)) {
60 .addReg(SrcReg, getKillRegState(KillSrc));
103 unsigned SrcReg, bool isKill,
133 .addReg(SrcReg, getKillRegState(isKill))
|
| AVRInstrInfo.h | 76 const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
79 MachineBasicBlock::iterator MI, unsigned SrcReg,
|
| /external/llvm/lib/Target/MSP430/ |
| MSP430InstrInfo.h | 56 const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
61 unsigned SrcReg, bool isKill,
|
| /external/llvm/lib/Target/Sparc/ |
| SparcInstrInfo.h | 83 const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
88 unsigned SrcReg, bool isKill, int FrameIndex,
|
| /external/llvm/lib/Target/XCore/ |
| XCoreInstrInfo.h | 65 const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
70 unsigned SrcReg, bool isKill, int FrameIndex,
|
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| Thumb2InstrInfo.h | 43 unsigned DestReg, unsigned SrcReg,
48 unsigned SrcReg, bool isKill, int FrameIndex,
|
| /external/swiftshader/third_party/LLVM/lib/Target/Alpha/ |
| AlphaInstrInfo.h | 47 unsigned DestReg, unsigned SrcReg,
51 unsigned SrcReg, bool isKill, int FrameIndex,
|
| /external/swiftshader/third_party/LLVM/lib/Target/CellSPU/ |
| SPUInstrInfo.h | 49 unsigned DestReg, unsigned SrcReg,
55 unsigned SrcReg, bool isKill, int FrameIndex,
|
| /external/swiftshader/third_party/LLVM/lib/Target/MSP430/ |
| MSP430InstrInfo.h | 57 unsigned DestReg, unsigned SrcReg,
62 unsigned SrcReg, bool isKill,
|
| /external/swiftshader/third_party/LLVM/lib/Target/PTX/ |
| PTXInstrInfo.cpp | 49 unsigned DstReg, unsigned SrcReg,
53 //assert(MRI.getRegClass(SrcReg) == MRI.getRegClass(DstReg) &&
60 addReg(SrcReg, getKillRegState(KillSrc));
71 unsigned DstReg, unsigned SrcReg,
81 MachineInstr *MI = BuildMI(MBB, I, DL, MCID, DstReg).addReg(SrcReg);
90 unsigned &SrcReg, unsigned &DstReg,
106 SrcReg = MI.getOperand(1).getReg();
302 unsigned SrcReg, bool isKill, int FrameIdx,
|
| /external/swiftshader/third_party/LLVM/lib/Target/Sparc/ |
| SparcInstrInfo.h | 80 unsigned DestReg, unsigned SrcReg,
85 unsigned SrcReg, bool isKill, int FrameIndex,
|
| /external/swiftshader/third_party/LLVM/lib/Target/XCore/ |
| XCoreInstrInfo.h | 66 unsigned DestReg, unsigned SrcReg,
71 unsigned SrcReg, bool isKill, int FrameIndex,
|
| /external/llvm/lib/CodeGen/ |
| OptimizePHIs.cpp | 104 unsigned SrcReg = MI->getOperand(i).getReg();
105 if (SrcReg == DstReg)
107 MachineInstr *SrcMI = MRI->getVRegDef(SrcReg);
125 SingleValReg = SrcReg;
|
| /external/llvm/lib/Target/Mips/ |
| MipsTargetStreamer.h | 119 void emitAddu(unsigned DstReg, unsigned SrcReg, unsigned TrgReg, bool Is64Bit,
121 void emitDSLL(unsigned DstReg, unsigned SrcReg, int16_t ShiftAmount,
134 void emitStoreWithImmOffset(unsigned Opcode, unsigned SrcReg,
138 void emitStoreWithSymOffset(unsigned Opcode, unsigned SrcReg,
|
