| /external/pcre/dist2/src/sljit/ |
| sljitNativeARM_T2_32.c | 161 #define SXTH 0xb200
713 return push_inst16(compiler, SXTH | RD3(dst) | RN3(arg2));
[all...] |
| sljitNativeARM_32.c | 122 #define SXTH 0xe6bf0070
[all...] |
| /external/swiftshader/third_party/LLVM/test/MC/Disassembler/ARM/ |
| thumb1.txt | 494 # SXTB/SXTH
497 # CHECK: sxth r3, r5
|
| thumb2.txt | [all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMScheduleSwift.td | 157 (instregex "SXTB", "SXTH", "SXTB16", "UXTB", "UXTH", "UXTB16",
[all...] |
| ARMInstrInfo.td | [all...] |
| /external/swiftshader/third_party/subzero/src/ |
| IceAssemblerARM32.h | 309 // Implements sxtb/sxth depending on type of OpSrc0.
|
| /external/v8/src/arm64/ |
| constants-arm64.h | 344 SXTH = 5,
[all...] |
| assembler-arm64.h | 587 // where <extend> is one of {UXTB, UXTH, UXTW, UXTX, SXTB, SXTH, SXTW, SXTX}.
1179 void sxth(const Register& rd, const Register& rn) { function in class:v8::internal::Assembler
[all...] |
| /external/vixl/test/aarch32/ |
| test-disasm-a32.cc | [all...] |
| test-assembler-cond-rd-operand-rn-a32.cc | 62 M(sxth) \
[all...] |
| test-assembler-cond-rd-operand-rn-ror-amount-a32.cc | 54 M(sxth) \
[all...] |
| test-assembler-cond-rd-operand-rn-ror-amount-t32.cc | 54 M(sxth) \
[all...] |
| /external/llvm/test/MC/ARM/ |
| basic-thumb-instructions.s | 638 @ SXTB/SXTH
641 sxth r3, r5
644 @ CHECK: sxth r3, r5 @ encoding: [0x2b,0xb2]
|
| /external/swiftshader/third_party/LLVM/test/MC/ARM/ |
| basic-thumb-instructions.s | 587 @ SXTB/SXTH
590 sxth r3, r5
593 @ CHECK: sxth r3, r5 @ encoding: [0x2b,0xb2]
|
| /external/swiftshader/third_party/subzero/tests_lit/llvm2ice_tests/ |
| 64bit.pnacl.ll | 958 ; ARM32: sxth r0, r0
1031 ; ARM32: sxth r0, r0
1172 ; ARM32: sxth
[all...] |
| /external/valgrind/none/tests/arm/ |
| v6intThumb.c | [all...] |
| v6intThumb.stdout.exp | 370 SXTH-16 0x2C8
371 sxth r1, r2 :: rd 0x00005927 rm 0x31415927, c:v-in 0, cpsr 0xc0000000 NZ
372 sxth r1, r2 :: rd 0xffff9597 rm 0x31419597, c:v-in 0, cpsr 0xc0000000 NZ
373 sxth r1, r2 :: rd 0x00005927 rm 0x31415927, c:v-in 1, cpsr 0xd0000000 NZ V
374 sxth r1, r2 :: rd 0xffff9597 rm 0x31419597, c:v-in 1, cpsr 0xd0000000 NZ V
375 sxth r1, r2 :: rd 0x00005927 rm 0x31415927, c:v-in 2, cpsr 0xe0000000 NZC
376 sxth r1, r2 :: rd 0xffff9597 rm 0x31419597, c:v-in 2, cpsr 0xe0000000 NZC
377 sxth r1, r2 :: rd 0x00005927 rm 0x31415927, c:v-in 3, cpsr 0xf0000000 NZCV
378 sxth r1, r2 :: rd 0xffff9597 rm 0x31419597, c:v-in 3, cpsr 0xf0000000 NZCV
[all...] |
| /art/test/551-checker-shifter-operand/src/ |
| Main.java | 312 /// CHECK: sxth
[all...] |
| /device/linaro/bootloader/edk2/ArmPkg/Library/ArmDisassemblerLib/ |
| ThumbDisassembler.c | 204 { "SXTH", 0xb200, 0xffc0, DATA_FORMAT5 },
[all...] |
| /external/llvm/lib/Target/AArch64/AsmParser/ |
| AArch64AsmParser.cpp | 989 ET == AArch64_AM::UXTH || ET == AArch64_AM::SXTH ||
[all...] |
| /external/llvm/test/CodeGen/ARM/ |
| atomic-ops-v8.ll | 616 ; CHECK-NEXT: sxth r[[OLDX:[0-9]+]], r[[OLD]]
729 ; CHECK-NEXT: sxth r[[OLDX:[0-9]+]], r[[OLD]]
[all...] |
| /external/vixl/doc/aarch64/ |
| supported-instructions-aarch64.md | 1257 ### SXTH ###
1261 void sxth(const Register& rd, const Register& rn)
[all...] |
| /external/vixl/src/aarch64/ |
| macro-assembler-aarch64.h | [all...] |
| /frameworks/compile/mclinker/lib/Target/Hexagon/ |
| HexagonEncodings.h | 379 { "Re16=#u6 ; Rd16=sxth(Rs16)",
859 { "Rx16=add(Rx16,#s7) ; Rd16=sxth(Rs16)",
[all...] |
