| /external/vixl/test/aarch64/traces/ |
| sim-usra-16b-2opimm-trace-aarch64.h | 1 // Copyright 2015, VIXL authors
|
| sim-usra-2s-2opimm-trace-aarch64.h | 1 // Copyright 2015, VIXL authors
|
| sim-usubl-2d-trace-aarch64.h | 1 // Copyright 2015, VIXL authors
[all...] |
| sim-usubl-4s-trace-aarch64.h | 1 // Copyright 2015, VIXL authors
|
| sim-usubl2-2d-trace-aarch64.h | 1 // Copyright 2015, VIXL authors
[all...] |
| sim-usubl2-4s-trace-aarch64.h | 1 // Copyright 2015, VIXL authors
|
| /art/compiler/optimizing/ |
| intrinsics_arm_vixl.cc | 57 using namespace vixl::aarch32; // NOLINT(build/namespaces)
59 using vixl::ExactAssemblyScope;
60 using vixl::CodeBufferCheckScope;
[all...] |
| /external/vixl/src/aarch32/ |
| macro-assembler-aarch32.cc | 1 // Copyright 2015, VIXL authors
36 namespace vixl { namespace
[all...] |
| /external/vixl/src/aarch64/ |
| macro-assembler-aarch64.cc | 1 // Copyright 2015, VIXL authors
31 namespace vixl { namespace
[all...] |
| /external/vixl/test/aarch32/ |
| test-assembler-cond-rd-memop-immediate-512-a32.cc | 1 // Copyright 2016, VIXL authors
47 namespace vixl { namespace
[all...] |
| test-assembler-cond-rd-memop-immediate-8192-a32.cc | 1 // Copyright 2016, VIXL authors
47 namespace vixl { namespace
[all...] |
| test-assembler-cond-rd-memop-rs-a32.cc | 1 // Copyright 2016, VIXL authors
47 namespace vixl { namespace
[all...] |
| test-assembler-cond-rd-memop-rs-shift-amount-1to31-a32.cc | 1 // Copyright 2016, VIXL authors
47 namespace vixl { namespace
[all...] |
| test-assembler-cond-rd-memop-rs-shift-amount-1to32-a32.cc | 1 // Copyright 2016, VIXL authors
47 namespace vixl { namespace
[all...] |
| test-assembler-cond-rd-operand-const-t32.cc | 1 // Copyright 2016, VIXL authors
47 namespace vixl { namespace
[all...] |
| test-assembler-cond-rd-operand-rn-a32.cc | 1 // Copyright 2016, VIXL authors
47 namespace vixl { namespace
[all...] |
| test-assembler-cond-rd-operand-rn-ror-amount-a32.cc | 1 // Copyright 2016, VIXL authors
47 namespace vixl { namespace
[all...] |
| test-assembler-cond-rd-operand-rn-ror-amount-t32.cc | 1 // Copyright 2016, VIXL authors
47 namespace vixl { namespace
[all...] |
| test-assembler-cond-rd-operand-rn-shift-amount-1to31-a32.cc | 1 // Copyright 2016, VIXL authors
47 namespace vixl { namespace
[all...] |
| test-assembler-cond-rd-operand-rn-shift-amount-1to31-t32-in-it-block.cc | 1 // Copyright 2016, VIXL authors
47 namespace vixl { namespace
[all...] |
| test-assembler-cond-rd-operand-rn-shift-amount-1to31-t32.cc | 1 // Copyright 2016, VIXL authors
47 namespace vixl { namespace
[all...] |
| test-assembler-cond-rd-operand-rn-shift-rs-a32.cc | 1 // Copyright 2016, VIXL authors
47 namespace vixl { namespace
[all...] |
| test-assembler-cond-rd-operand-rn-shift-rs-t32-in-it-block.cc | 1 // Copyright 2016, VIXL authors
47 namespace vixl { namespace
[all...] |
| test-assembler-cond-rd-operand-rn-shift-rs-t32.cc | 1 // Copyright 2016, VIXL authors
47 namespace vixl { namespace
[all...] |
| test-assembler-cond-rd-pc-operand-imm12-t32.cc | 1 // Copyright 2016, VIXL authors
47 namespace vixl { namespace
[all...] |
