| /external/vixl/test/aarch32/ |
| test-assembler-cond-rd-operand-rn-shift-rs-t32-narrow-out-it-block.cc | 1 // Copyright 2016, VIXL authors
47 namespace vixl { namespace
495 } // namespace vixl
|
| test-assembler-cond-rd-sp-operand-imm8-t32.cc | 1 // Copyright 2016, VIXL authors
47 namespace vixl { namespace
493 } // namespace vixl
|
| test-macro-assembler-cond-rd-rn-a32.cc | 1 // Copyright 2016, VIXL authors
51 namespace vixl { namespace
[all...] |
| test-macro-assembler-cond-rd-rn-pc-a32.cc | 1 // Copyright 2016, VIXL authors
51 namespace vixl { namespace
[all...] |
| test-macro-assembler-cond-rd-rn-t32.cc | 1 // Copyright 2016, VIXL authors
51 namespace vixl { namespace
[all...] |
| test-simulator-cond-rd-operand-rn-ror-amount-a32.cc | 1 // Copyright 2016, VIXL authors
113 namespace vixl { namespace
[all...] |
| test-simulator-cond-rd-operand-rn-ror-amount-t32.cc | 1 // Copyright 2016, VIXL authors
113 namespace vixl { namespace
[all...] |
| test-simulator-cond-rd-operand-rn-shift-amount-1to31-a32.cc | 1 // Copyright 2016, VIXL authors
113 namespace vixl { namespace
[all...] |
| test-simulator-cond-rd-operand-rn-shift-amount-1to31-t32.cc | 1 // Copyright 2016, VIXL authors
113 namespace vixl { namespace
[all...] |
| test-simulator-cond-rd-operand-rn-shift-amount-1to32-a32.cc | 1 // Copyright 2016, VIXL authors
113 namespace vixl { namespace
[all...] |
| test-simulator-cond-rd-operand-rn-shift-amount-1to32-t32.cc | 1 // Copyright 2016, VIXL authors
113 namespace vixl { namespace
[all...] |
| test-simulator-cond-rd-rn-rm-a32-ge.cc | 1 // Copyright 2016, VIXL authors
113 namespace vixl { namespace
701 } // namespace vixl
|
| test-simulator-cond-rd-rn-rm-a32-q.cc | 1 // Copyright 2016, VIXL authors
113 namespace vixl { namespace
685 } // namespace vixl
|
| test-simulator-cond-rd-rn-rm-a32-sel.cc | 1 // Copyright 2016, VIXL authors
113 namespace vixl { namespace
678 } // namespace vixl
|
| test-simulator-cond-rd-rn-rm-t32-ge.cc | 1 // Copyright 2016, VIXL authors
113 namespace vixl { namespace
701 } // namespace vixl
|
| test-simulator-cond-rd-rn-rm-t32-q.cc | 1 // Copyright 2016, VIXL authors
113 namespace vixl { namespace
685 } // namespace vixl
|
| test-simulator-cond-rd-rn-rm-t32-sel.cc | 1 // Copyright 2016, VIXL authors
113 namespace vixl { namespace
678 } // namespace vixl
|
| test-simulator-cond-rdlow-operand-imm8-t32.cc | 1 // Copyright 2016, VIXL authors
113 namespace vixl { namespace
[all...] |
| test-simulator-rd-rn-rm-a32.cc | 1 // Copyright 2016, VIXL authors
113 namespace vixl { namespace
[all...] |
| test-simulator-rd-rn-rm-t32.cc | 1 // Copyright 2016, VIXL authors
113 namespace vixl { namespace
[all...] |
| /external/vixl/tools/ |
| generate_tests.py | 3 # Copyright 2016, VIXL authors
33 From the VIXL toplevel directory run:
128 // C++ type used by VIXL to represent this operand.
|
| /art/test/626-checker-arm64-scratch-register/src/ |
| Main.java | 206 // resolver's scratch register pool (provided by VIXL) was in the
|
| /external/vixl/src/aarch64/ |
| debugger-aarch64.cc | 1 // Copyright 2014, VIXL authors
31 namespace vixl { namespace
754 char* line = ReadCommandLine("vixl> ", buffer, kMaxDebugShellLine);
[all...] |
| /external/vixl/test/aarch32/config/ |
| cond-rd-rn-operand-rm-t32.json | 1 // Copyright 2016, VIXL authors
|
| /external/vixl/test/aarch32/traces/ |
| assembler-cond-rdlow-rnlow-operand-immediate-t32-zero-rsbs.h | 1 // Copyright 2015, VIXL authors
|
